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Features
* High Performance, Low Power AVR(R) 8-Bit Microcontroller * Advanced RISC Architecture
- 120 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation Non-Volatile Program and Data Memories - 4K Bytes of In-System Programmable Program Memory Flash - 64 Bytes of In-System Programmable EEPROM - 256 Bytes of Internal SRAM - Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM - Data retention: 20 years at 85C/ 100 years at 25C(1) - Programming Lock for Software Security Peripheral Features - Two 8-Bit Timer/Counters with two PWM Channels, Each - Programmable Watchdog Timer with Separate On-chip Oscillator - On-Chip Analog Comparator - 10-bit ADC 4 Single-Ended Channels - Universal Serial Interface - Boost Converter Special Microcontroller Features - debugWIRE On-chip Debug System - In-System Programmable via SPI Port - External and Internal Interrupt Sources - Pin Change Interrupt on 16 Pins - Low Power Idle, ADC Noise Reduction and Power-Down Modes - Enhanced Power-On Reset Circuit - Programmable Brown-Out Detection Circuit - Internal Calibrated Oscillator - Temperature Sensor On Chip I/O and Packages - Available in 20-Pin SOIC and 20-Pin QFN/MLF - 16 Programmable I/O Lines Operating Voltage: - 0.7 - 1.8V (via On-Chip Boost Converter) - 1.8 - 5.5V (Boost Converter Bypassed) Speed Grade - Using On-Chip Boost Converter 0 - 4 MHz - External Power Supply 0 - 4 MHz @ 1.8 - 5.5V 0 - 8 MHz @ 2.7 - 5.5V Low Power Consumption - Active Mode, 1 MHz System Clock (Without Boost Converter) 400 A @ 3V - Power-Down Mode (Without Boost Converter) 150 nA @ 3V 1. See "Data Retention" on page 6 for details.
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8-bit Microcontroller with 4K Bytes In-System Programmable Flash and Boost Converter ATTINY43U Preliminary
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1. Pin Configurations
Figure 1-1. Pinout of ATTINY43U
SOIC
(T0/PCINT8) PB0 (OC0A/PCINT9) PB1 (OC0B/PCINT10) PB2 (T1/CLKO/PCINT11) PB3 (DI/OC1A/PCINT12) PB4 (DO/OC1B/PCINT13) PB5 (USCK/SCL/PCINT14) PB6 (INT0/PCINT15) PB7 VCC GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA7 (RESET/dW/PCINT7) PA6 (CLKI/PCINT6) PA5 (AIN1/PCINT5) PA4 (AIN0/PCINT4) PA3 (ADC3/PCINT3) PA2 (ADC2/PCINT2) PA1 (ADC1/PCINT1) PA0 (ADC0/PCINT0) VBAT LSW
QFN/MLF Top View
PB0 (T0/PCINT8) PA7 (RESET/dW/PCINT7) PA6 (CLKI) PA5 (AIN1/PCINT5) 15 14 13 12 11 6 7 8 9 10
PB1 (OC0A/PCINT9)
(OC0B/PCINT9) PB2
(T1/CLKO/PCINT11) PB3 (DI/OC1A/PCINT12) PB4 (DO/OC1B/PCINT13) PB5 (USCK/SCL/PCINT14) PB6
1 2 3 4 5
20 19 18 17 16
PA4 (AIN0/PCINT4) PA3 (ADC3/PCINT3) PA2 (ADC2/PCINT2) PA1 (ADC1/PCINT1) PA0 (ADC0/PCINT0)
NOTE: Bottom pad should be Soldered to ground.
1.1
1.1.1
Pin Descriptions
VCC Supply voltage.
1.1.2
GND Ground.
1.1.3
Port A (PA7:PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source
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(INT0/PCINT15) PB7
VCC GND LSW VBAT
capability except PA7 which has the RESET capability. To use pin PA7 as an I/O pin, instead of RESET pin, program (`0') RSTDISBL fuse. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has an alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in "Alternate Port Functions" on page 67. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 20-4 on page 158. Shorter pulses are not guaranteed to generate a reset. 1.1.5 Port B (PB7:PB0) Port B is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features as listed in Section 11.3 "Alternate Port Functions" on page 67. 1.1.6 LSW Boost converter external inductor connection. Connect to ground when boost converter is disabled permanently. 1.1.7 VBAT Battery supply voltage. Connect to ground when boost converter is disabled permanently.
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2. Overview
The ATTINY43U is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATTINY43U achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. Block Diagram
VCC RESET
VBAT LSW GND
BOOST CONVERTER
POWER SUPERVISION
POR BOD RESET
INTERNAL OSCILLATOR
CALIBRATED OSCILLATOR
WATCHDOG TIMER
TIMING AND CONTROL
PROGRAMMING LOGIC
PROGRAM COUNTER
MCU CONTROL REGISTER
PROGRAM FLASH
STACK POINTER
MCU STATUS REGISTER
INSTRUCTION REGISTER
SRAM
TIMER/ COUNTER0
INSTRUCTION DECODER
GENERAL PURPOSE REGISTERS
X Y Z
TIMER/ COUNTER1
CONTROL LINES
INTERRUPT UNIT
ANALOG COMPARATOR
ON-CHIP DEBUG
ALU
EEPROM
VOLTAGE REFERENCE
ISP INTERFACE
STATUS REGISTER
USI
ADC
DATA REGISTER PORT A
DIRECTION REG. PORT A
DATA REGISTER PORT B
DIRECTION REG. PORT B
DRIVERS PORT A
DRIVERS PORT B
PA7:0
PB7:0
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting
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architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATTINY43U provides the following features: 4K byte of In-System Programmable Flash, 64 bytes EEPROM, 256 bytes SRAM, 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit Timer/Counters with two PWM channels, Internal and External Interrupts, a 4-channel 10-bit ADC, Universal Serial Interface, a programmable Watchdog Timer with internal Oscillator, internal calibrated oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. A special feature of ATTINY43U is the built-in boost voltage converter, which provides 3V supply voltage from an external, low voltage. The device is manufactured using Atmel's high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATTINY43U AVR is supported by a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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3. About
3.1 Resources
A comprehensive set of development tools, drivers and application notes, and datasheets are available for download on http://www.atmel.com/avr.
3.2
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
3.3
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85C or 100 years at 25C.
3.4
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
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4. AVR CPU Core
4.1 Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.
4.2
Architectural Overview
Figure 4-1. Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash Program Memory
Program Counter
Status and Control
Instruction Register
32 x 8 General Purpose Registrers
Interrupt Unit Watchdog Timer
Indirect Addressing
Instruction Decoder
Direct Addressing
ALU
Control Lines
Analog Comparator
Timer/Counter 0
Data SRAM
Timer/Counter 1
Universal Serial Interface EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F.
4.3
ALU - Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories - arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the "Instruction Set" section for a detailed description.
4.4
Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.
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4.4.1
SREG - AVR Status Register
Bit 0x3F (0x5F) Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG
* Bit 7 - I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. * Bit 6 - T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. * Bit 5 - H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the "Instruction Set Description" for detailed information. * Bit 4 - S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two's Complement Overflow Flag V. See the "Instruction Set Description" for detailed information. * Bit 3 - V: Two's Complement Overflow Flag The Two's Complement Overflow Flag V supports two's complement arithmetics. See the "Instruction Set Description" for detailed information. * Bit 2 - N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 1 - Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information. * Bit 0 - C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the "Instruction Set Description" for detailed information.
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4.5
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: * One 8-bit output operand and one 8-bit result input * Two 8-bit output operands and one 8-bit result input * Two 8-bit output operands and one 16-bit result input * One 16-bit output operand and one 16-bit result input
Figure 4-2 on page 10 shows the structure of the 32 general purpose working registers in the CPU. Figure 4-2. AVR CPU General Purpose Working Registers
7 R0 R1 R2 ... R13 General Purpose Working Registers R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02
Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 4.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3 on page 11.
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Figure 4-3.
The X-, Y-, and Z-registers
15 XH 0 7 R26 (0x1A) XL 0 0
X-register
7 R27 (0x1B)
15 Y-register 7 R29 (0x1D) 15 Z-register 7 R31 (0x1F)
YH 0 7 R28 (0x1C) ZH 0 7 R30 (0x1E)
YL
0 0
ZL 0
0
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).
4.6
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer. The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure 5-2 on page 16. See Table 4-1 for Stack Pointer details. Table 4-1.
Instruction PUSH CALL ICALL RCALL POP RET RETI
Stack Pointer instructions
Stack pointer Decremented by 1 Decremented by 2 Incremented by 1 Incremented by 2 Description Data is pushed onto the stack Return address is pushed onto the stack with a subroutine call or interrupt Data is popped from the stack Return address is popped from the stack with return from subroutine or return from interrupt
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
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4.6.1
SPH and SPL -- Stack Pointer Register
Bit 0x3E (0x5E) 0x3D (0x5D) 15 SP15 SP7 7 Read/Write Read/Write Initial Value Initial Value R/W R/W
RAMEND RAMEND
14 SP14 SP6 6 R/W R/W
RAMEND RAMEND
13 SP13 SP5 5 R/W R/W
RAMEND RAMEND
12 SP12 SP4 4 R/W R/W
RAMEND RAMEND
11 SP11 SP3 3 R/W R/W
RAMEND RAMEND
10 SP10 SP2 2 R/W R/W
RAMEND RAMEND
9 SP9 SP1 1 R/W R/W
RAMEND RAMEND
8 SP8 SP0 0 R/W R/W
RAMEND RAMEND
SPH SPL
4.7
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 4-4 on page 12 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 4-4. The Parallel Instruction Fetches and Instruction Executions
T1 T2 T3 T4
clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch
Figure 4-5 on page 12 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 4-5. Single Cycle ALU Operation
T1 T2 T3 T4
clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back
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4.8
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in "Interrupts" on page 57. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction - RETI - is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
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Assembly Code Example
in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) ; store SREG value ; start EEPROM write ; disable interrupts during timed sequence
C Code Example
char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example
sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s)
C Code Example
_SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */
4.8.1
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.
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5. Memories
5.1 Overview
This section describes the different memories in ATTINY43U. The AVR architecture has two main memory spaces, the Data memory and the Program memory space. In addition, the ATTINY43U features an EEPROM Memory for data storage. All three memory spaces are linear and regular.
5.2
In-System Re-programmable Flash Program Memory
The ATTINY43U contains 4K byte On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 2048 x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATTINY43U Program Counter (PC) is 11 bits wide, thus addressing the 2048 Program memory locations. "Memory Programming" on page 139 contains a detailed description on Flash data downloading. Constant tables can be allocated within the entire Program memory address space (see the LPM - Load Program memory instruction description). Timing diagrams for instruction fetch and execution are presented in "Instruction Execution Timing" on page 12. Figure 5-1. Program Memory Map
Program Memory
0x0000
0x07FF
5.3
SRAM Data Memory
Figure 5-2 on page 16 shows how the ATTINY43U SRAM Memory is organized. The low Data memory locations address both the Register File, the I/O memory and the internal data SRAM, as follows: * The first 32 locations address the Register File * The next 64 locations address the standard I/O memory * The last 256 locations address the internal data SRAM
The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
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The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 256 bytes of internal data SRAM in ATTINY43U are all accessible through all these addressing modes. The Register File is described in "General Purpose Register File" on page 10. Figure 5-2. Data Memory Map
Data Memory
32 Registers 64 I/O Registers 0x0000 - 0x001F 0x0020 - 0x005F 0x0060
Internal SRAM (256 x 8) 0x15F
5.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-3 on page 16. Figure 5-3. On-chip Data SRAM Access Cycles
T1 T2 T3
clkCPU Address Data WR Data RD
Compute Address Address valid
Memory Access Instruction
Next Instruction
5.4
EEPROM Data Memory
The ATTINY43U contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
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Read
Write
the EEPROM Control Register. For a detailed description of Serial data downloading to the EEPROM, see "Serial Programming" on page 151. 5.4.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See "Preventing EEPROM Corruption" on page 19 for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. See "Atomic Byte Programming" on page 17 and "Split Byte Programming" on page 17 for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. 5.4.2 Atomic Byte Programming Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEAR Register and data into EEDR Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write operation. Both the erase and write cycle are done in one operation and the total programming time is given in Table 1. The EEPE bit remains set until the erase and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations. Split Byte Programming It is possible to split the erase and write cycle in two different operations. This may be useful if the system requires short access time for some limited period of time (typically if the power supply voltage falls). In order to take advantage of this method, it is required that the locations to be written have been erased before the write operation. But since the erase and write operations are split, it is possible to do the erase operations when the system allows doing time-critical operations (typically after Power-up). Erase To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Table 1). The EEPE bit remains set until the erase operation completes. While the device is busy programming, it is not possible to do any other EEPROM operations. 5.4.5 Write To write a location, the user must write the address into EEAR and the data into EEDR. If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger the write operation only (programming time is given in Table 1). The EEPE bit remains set until the write operation completes. If the location to be written has not been erased before write, the
5.4.3
5.4.4
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data that is stored must be considered as lost. While the device is busy with programming, it is not possible to do any other EEPROM operations. The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in "OSCCAL - Oscillator Calibration Register" on page 28. The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example
EEPROM_write: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set Programming mode ldi out r16, (0<; Set up address (r17) in address register out EEAR, r17 ; Write data (r19) to data register out EEDR,r19 ; Write logical one to EEMPE sbi EECR,EEMPE ; Start eeprom write by setting EEPE sbi EECR,EEPE ret
C Code Example
void EEPROM_write(unsigned char ucAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<18
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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example
EEPROM_read: ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_read ; Set up address (r17) in address register out EEAR, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in ret r16,EEDR
C Code Example
unsigned char EEPROM_read(unsigned char ucAddress) { /* Wait for completion of previous write */ while(EECR & (1<5.4.6
Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.
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5.5
I/O Memory
The I/O space definition of the ATTINY43U is shown in "Register Summary" on page 167. All I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. See the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The I/O and Peripherals Control Registers are explained in later sections.
5.5.1
General Purpose I/O Registers ATTINY43U contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
5.6
5.6.1
Register Description
EEAR - EEPROM Address Register
Bit 0x1E (0x3E) Read/Write Initial Value 7 R 0 6 R 0 5 EEAR5 R/W X 4 EEAR4 R/W X 3 EEAR3 R/W X 2 EEAR2 R/W X 1 EEAR1 R/W X 0 EEAR0 R/W X EEAR
* Bits 7:6 - Res: Reserved Bit These bits are reserved and will always read zero. * Bits 5:0 - EEAR[5:0]: EEPROM Address The EEPROM Address Register - EEAR - specifies the EEPROM address. The EEPROM data bytes are addressed linearly in the range 0...(64-1). The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.
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5.6.2
EEDR - EEPROM Data Register
Bit 0x1D (0x3D) Read/Write Initial Value 7 EEDR7 R/W 0 6 EEDR6 R/W 0 5 EEDR5 R/W 0 4 EEDR4 R/W 0 3 EEDR3 R/W 0 2 EEDR2 R/W 0 1 EEDR1 R/W 0 0 EEDR0 R/W 0 EEDR
* Bits 7:0 - EEDR[7:0]: EEPROM Data For the EEPROM write operation the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 5.6.3 EECR - EEPROM Control Register
Bit 0x1C (0x3C) Read/Write Initial Value 7 - R 0 6 - R 0 5 EEPM1 R/W X 4 EEPM0 R/W X 3 EERIE R/W 0 2 EEMPE R/W 0 1 EEPE R/W X 0 EERE R/W 0 EECR
* Bit 7 - Res: Reserved Bit These bits are reserved and will always read zero. For compatibility with future AVR devices, always write this bit to zero. After reading, mask out this bit. * Bit 6 - Res: Reserved Bit These bits are reserved and will always read zero. * Bits 5, 4 - EEPM1 and EEPM0: EEPROM Mode Bits The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 5-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 5-1.
EEPM1 0 0 1 1
EEPROM Mode Bits
EEPM0 0 1 0 1 Programming Time 3.4 ms 1.8 ms 1.8 ms - Operation Erase and Write in one operation (Atomic Operation) Erase Only Write Only Reserved for future use
* Bit 3 - EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming. * Bit 2 - EEMPE: EEPROM Master Program Enable The EEMPE bit determines whether writing EEPE to one will have effect or not.
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When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. * Bit 1 - EEPE: EEPROM Program Enable The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed. * Bit 0 - EERE: EEPROM Read Enable The EEPROM Read Enable Signal - EERE - is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register. 5.6.4 GPIOR2 - General Purpose I/O Register 2
Bit 0x15 (0x35) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 GPIOR2
5.6.5
GPIOR1 - General Purpose I/O Register 1
Bit 0x14 (0x34) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 GPIOR1
5.6.6
GPIOR0 - General Purpose I/O Register 0
Bit 0x13 (0x33) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 GPIOR0
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6. System Clock and Clock Options
6.1 Clock Systems and their Distribution
Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in "Power Management and Sleep Modes" on page 31. The clock systems are detailed below. Figure 6-1. Clock Distribution
General I/O Modules ADC CPU Core RAM Flash and EEPROM
clkADC clkI/O clkCPU clkFLASH
AVR Clock Control Unit
System Clock Prescaler
Reset Logic
Watchdog Timer
Source clock Clock Multiplexer
Watchdog clock Watchdog Oscillator
External Clock
Calibrated RC Oscillator
6.1.1
CPU Clock - clkCPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. I/O Clock - clkI/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that start condition detection in the USI module is carried out asynchronously when clkI/O is halted. Flash Clock - clkFLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.
6.1.2
6.1.3
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6.1.4
ADC Clock - clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
6.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 6-1. Device Clocking Options Select(1)
CKSEL3..0 0000 0010 0011 0001, 0100-1111
Device Clocking Option External Clock (see page 24) Calibrated Internal 8 MHz Oscillator (see page 25) Internal 128 kHz Oscillator (see page 26) Reserved Note:
1. For all fuses "1" means unprogrammed while "0" means programmed.
6.2.1
External Clock To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-2 on page 24. To run the device on an external clock, the CKSEL Fuses must be programmed to "0000" (see Table 6-2). Table 6-2. Crystal Oscillator Clock Frequency
CKSEL3..0 0000 Frequency 0 - 8 MHz
Figure 6-2.
External Clock Drive Configuration
EXTERNAL CLOCK SIGNAL
CLKI
GND
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When this clock source is selected, start-up times are determined by SUT Fuses as shown in Table 6-3. Table 6-3.
SUT1..0 00 01 10 11
Start-up Times for the External Clock Selection
Start-up Time from Power-down 6 CK 6 CK 6 CK Additional Delay from Reset 14CK 14CK + 4 ms 14CK + 64 ms Reserved Recommended Usage BOD enabled Fast rising power Slowly rising power
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the changes. Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to "Power Management and Sleep Modes" on page 31 for details. 6.2.2 Calibrated Internal 8 MHz Oscillator By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the user. See Table 20-2 on page 157 for more details. The device is shipped with the CKDIV8 Fuse programmed. See "System Clock Prescaler" on page 27 for more details. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 6-4. If selected, it will operate with no external components. During reset, hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table 20-2 on page 157. By changing the OSCCAL register from SW, see "OSCCAL - Oscillator Calibration Register" on page 28, it is possible to get a higher calibration accuracy than by using the factory calibration. The accuracy of this calibration is shown as User calibration in Table 20-2 on page 157. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section "Calibration Byte" on page 142. Table 6-4. Internal Calibrated RC Oscillator Operating Modes
CKSEL3..0 0010 Notes:
(1)
Nominal Frequency (MHz) 8.0
1. The device is shipped with this option selected.
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When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 6-5 below. Table 6-5.
SUT1..0 00 01 10(2) 11 Note:
Start-up times for Internal Calibrated RC Oscillator Clock Selection
Start-up Time from Power-down 6 CK 6 CK 6 CK Additional Delay from Reset (VCC = 5.0V) 14CK
(1)
Recommended Usage BOD enabled Fast rising power Slowly rising power
14CK + 4 ms 14CK + 64 ms Reserved
1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to ensure programming mode can be entered. 2. The device is shipped with this option selected.
6.2.3
Internal 128 kHz Oscillator The 128 kHz internal oscillator is a low power oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25C. This clock may be select as the system clock by programming the CKSEL Fuses to "11" as shown in Table 6-6 below. Table 6-6. 128 kHz Internal Oscillator Operating Modes
CKSEL3..0 0011 Nominal Frequency 128 kHz
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-7 below. Table 6-7.
SUT1..0 00 01 10 11 Note:
Start-up Times for the 128 kHz Internal Oscillator
Start-up Time from Power-down 6 CK 6 CK 6 CK Additional Delay from Reset 14CK
(1)
Recommended Usage BOD enabled Fast rising power Slowly rising power
14CK + 4 ms 14CK + 64 ms Reserved
1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to ensure programming mode can be entered.
6.2.4
Default Clock Source The device is shipped with CKSEL = "0010", SUT = "10", and CKDIV8 programmed. The default clock source is therefore the internal RC oscillator running at 8.0 MHz with the longest start-up time and an initial system clock prescale setting of 8, resulting in a 1 MHz system clock. The default setting ensures every user can make the desired clock source setting using any available programming interface.
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6.2.5
Clock Startup Sequence Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating cycles before it can be considered stable. To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after the device reset is released by all other reset sources. The section "System Control and Reset" on page 48 describes the start conditions for the internal reset. The delay (tTOUT) is timed from the Watchdog Oscillator and the number of cycles in the delay is set by the SUTn and CKSELn fuse bits. The available delays are shown in Table 6-8. Table 6-8. Number of Watchdog Oscillator Cycles
Typ Time-out (VCC = 3.0V) 0 ms 4.3 ms 69 ms Number of Cycles 0 512 8K (8,192)
Typ Time-out (VCC = 5.0V) 0 ms 4.1 ms 65 ms Note:
The frequency of the Watchdog Oscillator is voltage dependent as shown in TBD.
The main purpose of the delay is to keep the AVR in reset until VCC has risen to a sufficient level. The delay will not monitor the actual voltage and, hence, the user must make sure the delay time is longer than the VCC rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit ensures there is sufficient VCC before it releases the reset line, and the time-out delay can then be disabled. It is not recommended to disable the time-out delay without implementing a Brown-Out Detection circuit. The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from Power-down mode, VCC is assumed to be at a sufficient level and only the start-up time is included.
6.3
System Clock Prescaler
The ATTINY43U has a system clock prescaler, which means the system clock can be divided as described in section "CLKPR - Clock Prescale Register" on page 28. This feature can be used to lower system clock frequency and decrease the power consumption at times when requirements for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. Clock signals clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 20-4 on page 158.
6.3.1
Switching Time When changing prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than either the clock frequency corresponding to the previous setting or the clock frequency corresponding to the new setting. The ripple counter of the prescaler runs at the same frequency as the undivided clock, which may be higher than the CPU's clock frequency. Hence, even if it was readable, it is not possible to determine the state of the prescaler, and it is not possible to predict the exact time it takes to switch from one clock division to the other. From the time the CLKPS values are written, 27
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it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.
6.4
Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.
6.5
6.5.1
Register Description
OSCCAL - Oscillator Calibration Register
Bit 7 CAL7 Read/Write Initial Value R/W 6 CAL6 R/W 5 CAL5 R/W 4 CAL4 R/W 3 CAL3 R/W 2 CAL2 R/W 1 CAL1 R/W 0 CAL0 R/W OSCCAL
Device Specific Calibration Value
* Bits 7:0 - CAL[7:0]: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency as specified in Table 20-2 on page 157. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 202 on page 157. Calibration outside that range is not guaranteed. Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail. The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80. The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. 6.5.2 CLKPR - Clock Prescale Register
Bit 7
CLKPCE
6
-
5
-
4
-
3
CLKPS3
2
CLKPS2
1
CLKPS1
0
CLKPS0 CLKPR
Read/Write Initial Value
R/W 0
R 0
R 0
R 0
R/W
R/W
R/W
R/W
See Bit Description
* Bit 7 - CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is 28
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cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. * Bits 3:0 - CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is affected. The division factors are given in Table 6-9. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to "0000". If CKDIV8 is programmed, CLKPS bits are reset to "0011", giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 6-9.
CLKPS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Clock Prescaler Select
CLKPS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CLKPS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CLKPS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock Division Factor 1 2 4 8 16 32 64 128 256 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
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Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.
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7. Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application's requirements. When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes. See "Software BOD Disable" on page 32 for more details.
7.1
Sleep Modes
Figure 6-1 on page 23 presents the different clock systems in ATTINY43U, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 below shows the different sleep modes and their wake-up sources. Table 7-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains Oscillators Main Clock Source Enabled Wake-up Sources SPM/EEPROM Ready
INT0 and Pin Change
Sleep Mode Idle ADC Noise Reduction Power-down Note:
X
X X
X X
X X
(1)
X X
X X
X
X(1)
1. For INT0, only level interrupt.
To enter any of the sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM1:0 bits in the MCUCR Register select which sleep mode (Idle, ADC Noise Reduction or Power-down) will be activated by the SLEEP instruction. See Table 7-2 on page 34 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Note that if a level triggered interrupt is used for wake-up the changed level must be held for some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See "External Interrupts" on page 58 for details. 7.1.1 Idle Mode When the SM1:0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
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Watchdog Interrupt X X X
Other I/O
clkFLASH
clkCPU
clkADC
ADC
clkIO
31
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the "ACSR - Analog Comparator Control and Status Register" on page 113. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 7.1.2 ADC Noise Reduction Mode When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the Watchdog to continue operating (if enabled). This sleep mode halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode. 7.1.3 Power-Down Mode When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode halts all generated clocks, allowing operation of asynchronous modules only.
7.2
Software BOD Disable
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see Table 19.2 on page 140), the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible for software to disable the BOD in Power-Down Mode (see "Power-Down Mode" on page 32). The sleep mode power consumption will then be at the same level as when BOD is globally disabled by fuses. If disabled by software, the BOD is turned off immediately after entering the sleep mode and automatically turned on upon wake-up. This ensures safe operation in case the VCC level has dropped during the sleep period. When the BOD has been disabled the wake-up time from sleep mode will be the same as the wake-up time from RESET. This is in order to ensure the BOD is working correctly before the MCU continues executing code. BOD disable is controlled by bit 7 (BODS -- BOD Sleep) of MCU Control Register, see "MCUCR - MCU Control Register" on page 34. Writing this bit to one turns off the BOD in Power-Down Mode, while a zero in this bit keeps BOD active. The default setting is zero, i.e. BOD active. Writing to the BODS bit is controlled by a timed sequence and an enable bit, see "MCUCR - MCU Control Register" on page 34.
7.3
Power Reduction Register
The Power Reduction Register (PRR), see "PRR - Power Reduction Register" on page 35, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozenand the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the
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peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped
7.4
Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device's functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.
7.4.1
Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. See "Analog to Digital Converter" on page 115 for details on ADC operation. Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. See "Analog Comparator" on page 112 for details on how to configure the Analog Comparator. Brown-out Detector If the Brown-out Detector is not needed in the application, this module should be turned off. If the Brown-out Detector is enabled it will be active in all sleep modes and, hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. See "Brown-out Detection" on page 50 and "Software BOD Disable" on page 32 for details on how to configure the Brown-out Detector. Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. See "Internal Voltage Reference" on page 51 for details on the start-up time. Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. See "Watchdog Timer" on page 51 for details on how to configure the Watchdog Timer.
7.4.2
7.4.3
7.4.4
7.4.5
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7.4.6
Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important thing is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. See the section "Digital Input Enable and Sleep Modes" on page 66 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an analog signal level close to VCC/2, the input buffer will use excessive power. For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to VCC/2 on an input pin can cause significant current even in active mode. Digital input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). See "DIDR0 - Digital Input Disable Register 0" on page 130 for details.
7.5
7.5.1
Register Description
MCUCR - MCU Control Register The MCU Control Register contains control bits for power management.
Bit 0x35 (0x55) Read/Write Initial Value 7 BODS R/W 0 6 PUD R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 BODSE R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR
* Bit 7 - BODS: BOD Sleep The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 7-1 on page 31. Writing to the BODS bit is controlled by a timed sequence and an enable bit, BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to zero within four clock cycles. The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles. * Bit 5 - SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer's purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. * Bits 4, 3 - SM[1:0]: Sleep Mode Select Bits 2:0 These bits select between the three available sleep modes as shown in Table 7-2 below. Table 7-2.
SM1 0
Sleep Mode Select
SM0 0 Sleep Mode Idle
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Table 7-2.
SM1 0 1 1
Sleep Mode Select
SM0 1 0 1 Sleep Mode ADC Noise Reduction Power-down Reserved
* Bit 2 - BODSE: BOD Sleep Enable BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence. 7.5.2 PRR - Power Reduction Register
Bit 0x00 (0x20) Read/Write Initial Value
7 PRE2 R 0
6 PRE1 R 0
5 PRE0 R 0
4 - R 0
3 PRTIM1 R/W 0
2 PRTIM0 R/W 0
1 PRUSI R/W 0
0 PRADC R/W 0 PRR
* Bits 7:5 - PRE[2:0]: Prepared Read Enable These bits are used for prepared read operations. See sections "Software Control of Boost Converter" on page 42 and "ADCSRB - ADC Control and Status Register B" on page 47. * Bit 4 - Res: Reserved Bit This bit is reserved and will always read zero. * Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. * Bit 2 - PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. * Bit 1 - PRUSI: Power Reduction USI Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When waking up the USI again, the USI should be re-initialized to ensure proper operation. * Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.
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8. Power Supply and On-Chip Boost Converter
In order to work properly microcontrollers typically require a supply voltage level that can not be provided by battery packs of less than two or three battery cells. This constraint adds to size, cost and complexity of the design. The integrated boost converter of ATTINY43U bridges the gap between minimum supply voltage of the device and typical output voltages of single-cell standard, alkaline, Lithium, NiCd or NiMH batteries. The boost converter enables the device to be powered from a source with a supply voltage well below 1V. A block diagram illustrating the use of the boost converter is shown in Figure 8-1, below. Figure 8-1. Block Diagram of Boost Converter Usage.
VCC
ATTINY43U
VBAT VIN 16 I/O
EXTERNAL COMPONENTS
LSW
REGULATOR
MCU
GND
8.1
Overview
A boost converter is a device that converts a DC voltage to a higher level. The integrated boost converter of ATTINY43U provides the microcontroller (and its peripherals) with a fixed supply voltage, generated from an external supply of lower voltage. The ATTINY43U boost converter is a switching type, step-up converter that uses an external inductor, a diode and bypass capacitors. The boost converter is self-sufficient, completely independent and does not need any control from the MCU. The converter starts automatically as soon as there is sufficient voltage at the VBAT pin. See Table 20-7 on page 159 for electrical characteristics. The microcontroller starts as soon as the regulated output of the boost converter rises above power-on and brown-out reset levels (if enabled), as described in section "System Control and Reset" on page 48. After the MCU is released from reset and has started running the application software can then measure the battery voltage and decide if there is sufficient voltage to continue operation. The boost converter continuously switches between storing energy in and draining energy from the external inductor. During the charge phase the current through the inductor ramps up at a rate determined by the converter input voltage. During the discharge phase energy stored in the inductor is released to the load and the current in the inductor ramps down at a rate determined by the difference between the input and output voltages. The boost converter requires some external components to operate. See Figure 8-2 on page 37 for component placement. The circuit is completed by inserting an inductor between node VIN and pin LSW, and a Schottky diode between pins LSW and VCC. In addition, an input capacitor and external bypass capacitor from VCC to GND are typically required. See "Typical Applications" on page 46 for more details.
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Figure 8-2.
Typical Connection of Boost Converter.
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 VCC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 VBAT LSW
R1
VIN
C4
C3
GND
C2 L1
C1
D1
When the boost converter is not connected the microcontroller can be powered directly from an external source and is then subject to the standard supply voltage limits defined in "Electrical Characteristics" on page 155. It is recommended to disable the Brown-Out Detection (BOD) circuit when using the integrated boost converter. This is because supply voltage of the microcontroller can drop to lowest BOD levels during regular operation. See "Brown-out Detection" on page 50.
8.2
Modes of Operation
The boost converter has three main modes of operation; Stop, Start, and Active. Operation begins from Stop Mode and is transferred to Start Mode when input voltage, VBAT, is sufficiently high for stable operation. When the converter has managed to raise the output voltage, VCC, to a sustainable level control is then transferred to the main mode of operation, Active Mode. The modes of operation are illustrated in Figure 8-3, below. Figure 8-3. Operating Modes of Boost Converter.
ENTRY
VS
P TO
STOP MODE
<
BA T
V BA
A MW IR F
RE
T
V
V BAT
< VS
> VS
TART
REGULATED
f(ILOAD )
P TO
ACTIVE MODE
LOW CURRENT
V CC < VBOO
f(ILOAD )
ST
VC > C VBOOST
START MODE
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8.2.1
Stop Mode The boost converter enters Stop Mode (see Figure 8-3 on page 37 for modes of operation) when input voltage ,VBAT, is below the shutdown voltage, VSTOP (see Table 20-7 on page 159). Alternatively, the boost converter enters Stop Mode when instructed by firmware to do so. In this mode of operation the boost converter is not active and current consumption is decreased to a minimum. This is in order to prevent battery discharge and to avoid battery damage. The voltage at the converter output, VCC, has no effect in this mode. The converter monitors the voltage of the input pin, VBAT, and waits for it to rise above the start voltage, VSTART (see Table 20-7 on page 159). When there is sufficient voltage at the input the converter exits Stop Mode and enters Start Mode.
8.2.2
Start Mode The converter switches from Stop Mode to Start Mode (see Figure 8-3 on page 37) as soon as the input voltage, VBAT, goes above the start voltage, VSTART (see Table 20-7 on page 159). Alternatively, the boost converter switches from Active Mode to Start Mode when the output voltage drops below VBOOST. In this mode of operation the boost converter pumps up the VCC voltage by switcing at a 50% duty cycle and high frequency, until it reaches VBOOST. All loads should be disconnected during this stage. The boost converter is designed to remain in Start Mode for a short moment, but it is optimised to bring the microcontroller on line, only. If there are additional loads connected to the VCC pin the boost converter may not reach the VCC voltage required to go into Active Mode.
8.2.3
Active Mode The converter enters Active Mode of operation (see Figure 8-3 on page 37) when both input and output voltages are sufficiently high. This means that VBAT is above VSTART and VCC is above VBOOST. If input voltage drops below VSTOP or output voltage drops below VBOOST the converter will exit Active Mode. Alternatively, firmware can force the boost converter to exit Active Mode and enter Stop Mode. In this mode of operation, the boost converter keeps VCC within limits given in Table 20-7 on page 159 by constantly adjusting the duty cycle between energy charge and discharge phases. The duty cycle is affected mainly by input voltage, VBAT, load current, ILOAD, and temperature. By default, the boost converter operates in Active Regulated Mode but when load current drops sufficiently low it will enter Active Low Current Mode, as explained in "Output Voltage versus Load Current" . In Active Low Current Mode current consumption is minimised on the expense of output voltage regulation.
8.2.4
Examples Figure 8-4 illustrates operating modes and input and output voltages of the boost converter. As input voltage, VBAT, rises above VSTART (see "Boost Converter Characteristics" on page 159) the converter enters Start Mode and output voltage, VCC, begins to rise. At VBOOST output voltage the converter exits Start Mode and goes into Active Mode. When output voltage exceeds the power-on threshold VPOT (see "System and Reset Characteristics" on page 158) the microcontroller is released from reset.
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Figure 8-4.
Input and Output Voltages of Boost Converter.
VCC
VBAT
VPOT VSTART VBOOST VSTOP t CONVERTER: MCU CORE:
STOP RESET ACTIVE ACTIVE STOP RESET
When input voltage VBAT falls below VSTOP the converter enters Stop Mode and output voltage VCC begins to fall. When converter output voltage, i.e. the supply voltage of the microcontroller, falls below VPOT the MCU will go into reset. Figure 8-5 illustrates how the boost converter output changes with load current. As converter output voltage rises above the power-on threshold the microcontroller is brought on-line and current consumption steps up to a level sufficiently high for the converter to remain in Active Regulated Mode of operation. Figure 8-5.
V/A VCCMAX VCCNOM VCC
Output Voltage vs. Load Current of Boost Converter.
VCCMIN
ILOAD
IMS
MODE:
t
ACTIVE, REGULATED LOW CURRENT MODE REGULATED
Note:
The figure is not to scale. Typically, the switching time (rising voltage) is measured in hundreds of microseconds and idle time (falling voltage) is measured in seconds.
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As current consumption goes below IMS (see Figure 8-5) the converter goes from Active Regulated Mode to Active Low Current Mode. After this, the more the load current is decreased the longer the discharge time of the output capacitor, i.e. the time when the converter is not switching, will be. Similarly, the charge time, i.e. the time when the converter is switching, will be shorter. Note that in Active Low Current Mode only the last part of the rising/switching slope is changed. Charge time can be minimised by forcing the device into Full Duty Cycle mode of operation (see "Full Duty Cycle" on page 41). When load current increases above IMS the converter goes back to Active Regulated Mode.
8.3
Output Voltage versus Load Current
The output voltage of the boost converter depends on the amount of load and method of duty cycle control. In Active Mode the boost converter operates in one of two sub-modes called (Active) Regulated Mode and (Active) Low Current Mode. In Regulated Mode the emphasis is on maintaining a stable output voltage, while in Low Current Mode the emphasis is on minimising current consumption. The converter always enters Active Regulated Mode at first and switches to Low Current Mode automatically when required but it is possible to design the application such that the converter always stays in Active Regulated Mode. The boost converter goes from Active Regulated Mode to Active Low Current Mode when the duty cycle reaches its minimum and the output voltage reaches its maximum. At this point the converter stops switching and the output voltage starts to fall. The converter starts switching again when the output voltage has fallen to the low limit defined for Low Current Mode. If load current increases sufficiently the converter will go back from Active Low Current Mode to Active Regulated Mode. See Figure 21-1 on page 165. The boost converter goes back to Start Mode if output voltage drops below VBOOST, and starts over from Stop Mode if input voltage drops below VSTOP, or when instructed by firmware to do so.
8.3.1
Active Regulated Mode This is the default method of operation in Active Mode. The converter will remain in this mode provided that load current is sufficiently high. See "Active Low Current Mode" on page 41. In this mode of operation the output voltage is constantly regulated. This means a stable output voltage with a low amplitude, high frequency ripple superimposed. See Figure 8-6 and Table 207 on page 159. The firmware can instruct the converter to leave this mode and enter Stop Mode. See "Software Control of Boost Converter" on page 42.
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Figure 8-6.
Typical Output Voltage of Boost Converter in Active Regulated Mode.
VCC
ACTIVE REGULATED MODE
OD
E
STA
RT M
VRPP
fSW
t
8.3.2
Active Low Current Mode The boost converter enters Active Low Current Mode from Active Regulated Mode when output voltage reaches its maximum and duty cycle is at its minimum. In practice, this means that the load current drops below a threshold. The threshold varies with converter input voltage and temperature but a typical plot is shown in Figure 21-1 on page 165. From Figure 21-1 on page 165 can be seen that at low input voltages (VBAT typically below 1.0V) and high load currents (ILOAD typically above 0.6mA) the boost converter will never enter Low Current Mode. Using Full Duty Cycle mode the boost converter can be forced to enter Active Low Current Mode at input voltages lower than those shown in Figure 21-1 on page 165. See "Full Duty Cycle" on page 41. In Low Current Mode the boost converter stops switching and reduces current consumption to a minimum, while still remaining active. Provided there are no external loads active the boost converter enters Low Current Mode automatically when the microcontroller goes into Power Down Mode (see "Sleep Modes" on page 31). In this mode of operation the converter periodically reaches its duty cycle low limit. When this happens the converter stops switching and the output voltage starts dropping. The converter starts switching again when the output voltage has decreased to the low limit of Active Low Current Mode. This results in a periodical pattern as illustrated in Figure 8-5 on page 39. If the output voltage, VCC, drops below VBOOST (due to an overload or a short circuit) the converter goes back to Start Mode. In addition, the firmware can instruct the converter to leave this mode and enter Stop Mode. See "Software Control of Boost Converter" on page 42.
8.3.3
Full Duty Cycle By default, the boost converter keeps VCC within limits by controlling the duty cycle of the switching waveform. It is possible to bypass the duty cycle regulation and lock the duty cycle at its maximum, resulting in a VCC voltage that quickly ramps up to the maximum limit and then starts dropping when the boost converter enters Low Current Mode. See Figure 8-7, below.
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Figure 8-7.
Typical Output Voltage of Boost Converter at Constant Full Duty Cycle.
VCC
FDC = ON FDC = OFF
FULL
See section "Software Control of Boost Converter" on page 42 for instructions on how to turn on and off duty cycle control. The use of Full Duty Cycle mode is recommended only at low load currents.
8.4
Overload Behaviour
The output is considered overloaded when the load current, ILOAD, exceeds the maximum given in Table 20-7 on page 159. During an overload condition the boost converter operates at maximum duty cycle and can no longer regulate VCC. If the overload condition prevails the output voltage will drop as load current increases. If VCC drops below its minimum level the converter will switch to Start Mode. In Start Mode the converter has a low load current capability, which means nearly all overload current will be drained straight from the battery (or other power source) via the inductor and the diode. The resistance of the inductor is typically very low and, provided the voltage of the power source remains constant, the output voltage during overload will stabilise to battery voltage, VBAT, minus the forward voltage drop, VF, of the diode used.
8.5
Software Control of Boost Converter
The boost converter is an independent hardware module that requires no interaction by the microcontroller, although some features can be controlled by firmware. Features that can be controlled by firmware are described in the following sections.
8.5.1
Stopping the Boost Converter The device firmware can stop the boost converter on demand. When issued a stop signal, the boost converter will exit Active Mode and enter Stop Mode, as illustrated in Figure 8-3 on page 37. This procedure allows the device to read true battery voltage using the on-board ADC, assess if the voltage is sufficient for the selected battery chemistry and then control the boost converter accordingly.
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VA RI A
DUTY CYCLE
BL E
To stop the boost converter, follow the below procedure: 1. Write 110x xxxx to the Power Reduction Register, PRR 2. Within 3 clock cycles of the above, write 10xx xxxx to PRR 3. Within 4 clock cycles of the first step, write 01xx xxxx to PRR 8.5.2 Switching to Full Duty Cycle Mode of Operation When duty cycle control is disabled the output voltage of the boost converter will rise as fast as possible, resulting in a minimum switching time and a maximum idle time for the converter. To turn on Full Duty Cycle (FDC) mode, follow the below procedure: 1. Write 110x xxxx to the Power Reduction Register, PRR 2. Within 3 clock cycles of the above, write 10xx xxxx to PRR 3. Within 4 clock cycles of the first step, write 111x xxxx to PRR 8.5.3 Switching to Normal (Variable Duty Cycle) Mode of Operation To return duty cycle control to the boost converter, follow the below procedure: 1. Write 111x xxxx to the Power Reduction Register, PRR
8.6
Component Selection
Refer to Figure 8-2 on page 37 for component placement and numbering.
8.6.1
Inductor Low inductance increases peak currents of the inductor, creating more interference noise and lowering the overall efficiency of the converter. Too high inductance values force the converter into non-stable operation. The boost converter has been optimized for a certain size inductance, L, and may not work reliably if other inductance values are used. See "Boost Converter Component Values" on page 45. The inductor must be able to tolerate the following input current: V CC x I LOAD I IN = -------------------------------V BAT x
... where is the efficiency of the converter at given voltages and load current. See "Boost Converter Efficiency vs. Load Current and VBAT Voltage" on page 166. The inductor must also be able to tolerate short peak currents. At steady state, i.e. when the converter has stabilised after a constant load current has been introduced, the peak current is calculated as follows: V BAT x T S x D I PEAK = ----------------------------------L
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... where D is the duty cycle and TS the switching period of the boost converter. See "Boost Converter Characteristics" on page 159 for limits. The steady-state duty cycle is calculated as follows: V CC 1 D = ------------ - -- x I LOAD -V 2
BAT
Overall efficiency of the boost converter is also affected by the resistance of the inductor. 8.6.2 Diode It is recommended to use a Schottky diode with forward voltage, VF, and reverse leakage current, IR, values as low as possible. This is because converter efficiency mainly depends on the forward voltage of the diode when ILOAD is at maximum and VBAT is at minimum. It should be noted that the reverse leakage current easily becomes a dominant factor, especially in Active Low Current Mode. For reference, see converter current consumption during Low Current Mode in Table 20-7 on page 159. The diode is subject to peak currents the same magnitude as the inductor. See "Inductor" on page 43. It should be noted that reverse leakage current is a highly temperature dependent variable. 8.6.3 Input Capacitors A voltage drop occurs between the voltage source and inductor L1 because voltage sources are not ideal and tracks have a non-zero resistance. The voltage drop is application specific and depends on the quality of the voltage source, inductor current, track size and track length. Capacitor C1 counteracts the voltage drop by providing energy to the inductor during high peak currents. The highest inductor peak currents are reached at highest load current and lowest VBAT of the application. The input capacitor stabilises the input voltage and guarantees stable operation at all load currents. The size of the capacitor can be decreased if load currents remain low, or if a voltage supply with low internal resistance is available. Also, a good low-pass filter design (see section "RC Filter" below) reduces the size requirements of the capacitor. 8.6.4 RC Filter A secondary input capacitor, C2, and a series input resistor, R1, are recommended. Together they form a Low-Pass Filter (LPF), the purpose of which is to reduce the voltage ripple at the VBAT pin. The corner frequency of the filter can be calculated as follows: 1 f LPF = -------------------------------------2 x x R1 x C2
Component values are application specific and depend on the stability of the supply voltage. The LPF reduces voltage ripple at the VBAT pin and helps to prevent the boost converter unintentionally entering Stop Mode.
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Too high resistor values may lead to Start Mode failures. See "Boost Converter Component Values" on page 45 for component recommendations and limits. Capacitor C2 should be located close to the device. 8.6.5 Output Capacitors An output capacitor, C3, is required to keep the output voltage stable at times when energy is transferred to the inductor. It is recommended to use a capacitor with high capacitance and low Equivalent Series Resistance, ESR. A large capacitance helps to reduce the voltage ripple at the output and a low ESR reduces voltage ripple and helps to keep the temperature of the capacitor within limits. The recommended capacitance at a given, steady-state load is calculated as follows: I LOAD x T S x D C OUT = ------------------------------------V PP
... where TS is the switching frequency of the boost converter, VPP is the allowed voltage ripple and D is the duty cycle, calculated as shown in "Inductor" on page 43. The recommended ESR is calculated as follows: V PP ESR -------------I PEAK
A secondary output capacitor, C4, is recommended and should be placed close to the device. 8.6.6 Summary The table below summarises recommended component values for a typical application. Table 8-1.
Component
Boost Converter Component Values
Recommended Value Min (2) 1F
(1)
Max (2)
C1 C2 C3 C4 D1 L1 R1
Note:
C = 4.7F C = 100nF
C = 22F, ESR < 100m C = 100nF IR = 1A @ 25C, VF = 0.5V @ 1A L = 15H 20%, IMAX = 700mA, R < 150m R = 680 (1)
10F 100nF 100nF
15H
15H 1k
1. With these values the LPF provides a 32dB attenuation at the switching frequency of the boost converter while permitting a supply voltage ripple of about 200mV 2. Application specific limits may be tighter
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8.7
Typical Applications
A typical use of the boost converter is illustrated in Figure 8-2 on page 37. Components can be optimized depending on the type of application. Table 8-2, below, presents recommendations for three different types of applications (cost effective, high output current and long battery life). All values are guidelines, only. Table 8-2.
Symbol L1 D1 R1 C1 C2 C3 C4 Notes:
Recommended Components and Values for Various Designs
Component Inductor Schottky diode Resistor Input Capacitor Secondary Input Cap. Output Capacitor Secondary Output Cap. Cost Effective 15 10MQ100N 680 1 (4) 100 10
(5)
High Current 15
(1) (2)
Battery Life 15
(1) (3)
Unit H
10BQ015 680 4.7 100 22 22
10BQ040 680 4.7 100 22 22
F nF F nF
-
1. Low ESR required. 2. High reverse leakage current, increases current consumption. 3. The diode is the largest individual contributor to battery life. The example diode keeps the boost converter running and maintains a reasonable efficiency level. 4. Depends on internal resistance of power supply. 5. Depends on load current. May not be sufficient for maximum current rating.
8.8
Characteristics
Electrical characteristics of the boost converter are given in Table 20-7 on page 159. Typical characteristics can be found under section "Boost Converter" on page 165.
8.9
Potential Limitations
When the device is powered via the boost converter some usage limitiations may apply. For example, the highest allowed operating frequency of the device depends on supply voltage (see "Speed Grades" on page 156) and the boost converter output voltage varies within the limits given in Table 20-7 on page 159. This means that if the design allows the boost converter to go into Active Low Current Mode the supply voltage will drop periodically, affecting the maximum allowed operating frequency. Provided the load current remains sufficiently high the boost converter will never enter Active Low Current Mode and the supply voltage will remain high enough to run the device at higher frequencies. The boost converter status bit BS can be used to determine if the boost converter is in Low Current Mode (see "ADCSRB - ADC Control and Status Register B" on page 47). Since the entire device is powered from the boost converter output variations will show in all peripherals. This means that, for example, high levels of I/O pins may vary with supply voltage.
8.10
Bypassing the Boost Converter
It is possible to bypass and disable the boost converter so that the device can be powered directly from an external supply. To force the boost converter into Stop Mode, connect pin VBAT to ground and provide the device with supply directly to the VCC pin. To permanently disable the
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boost converter, connect pins V BAT and LSW to ground and provide the device with supply directly to the VCC pin.
8.11
8.11.1
Register Description
ADCSRB - ADC Control and Status Register B
Bit 0x03 (0x23) Read/Write Initial Value 7 BS R 0 6 ACME R/W 0 5 - R/W 0 4 ADLAR R/W 0 3 - R/W 0 2 ADTS2 R/W 0 1 ADTS1 R/W 0 0 ADTS0 R/W 0 ADCSRB
* Bit 7 - BS: Boost Status The BS bit can be used to identify silent periods of the boost converter. When this bit is one the boost converter is active and switching, i.e. it is either in Active Regulated Mode, or in the switching period of Active Low Current Mode. When this bit is zero the boost converter is not switching, i.e. it is either in Stop Mode or in the non-switching period of Active Low Current Mode. Alternatively, the BS bit can be programmed to return the state of the duty cycle controller, as follows: 1. Write 11xx xxxx to register PRR 2. Within 3 clock cycles of the above, write 10xx xxxx to register PRR 3. Wait (issue a single-cycle no operation) 4. Within 5 clock cycles of first write, read the BS bit If the BS bit now is zero the converter is operating in normal duty cycle control mode. If the bit is one the converter is working in full duty cycle mode.
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9. System Control and Reset
9.1 Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP - Relative Jump - instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 9-1 shows the reset logic. Table 20-4 on page 158 defines the electrical parameters of the reset circuitry. Figure 9-1. Reset Logic
DATA BUS
MCU Status Register (MCUSR) PORF BORF EXTRF WDRF CK Delay Counters TIMEOUT
Power-on Reset Circuit
BODLEVEL [2..0] Pull-up Resistor
SPIKE FILTER
Brown-out Reset Circuit
Watchdog Oscillator
Clock Generator
CKSEL[1:0] SUT[1:0]
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in "Clock Sources" on page 24.
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9.2
Reset Sources
The ATTINY43U has four sources of reset: * Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT). * External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled. * Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. * Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.
9.3
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 20-4 on page 158. The POR is activated whenever VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay, when VCC decreases below the detection level. Figure 9-2.
VCC
MCU Start-up, RESET Tied to VCC
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
Figure 9-3.
VCC
MCU Start-up, RESET Extended Externally
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
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9.4
External Reset
An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer than the minimum pulse width (see Table 20-4 on page 158) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage - VRST - on its positive edge, the delay counter starts the MCU after the Time-out period - tTOUT - has expired. Figure 9-4.
CC
External Reset During Operation
9.5
Brown-out Detection
ATTINY43U has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT- in Figure 9-5 on page 50), the Brown-out Reset is immediately activated. When VCC increases above the trigger level (VBOT+ in Figure 9-5 on page 50), the delay counter starts the MCU after the Timeout period tTOUT has expired. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in Table 20-4 on page 158. Figure 9-5. Brown-out Reset During Operation
VCC VBOTVBOT+
RESET
TIME-OUT
tTOUT
INTERNAL RESET
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It is recommended to disable the BOD when using the integrated boost converter. See "Power Supply and On-Chip Boost Converter" on page 36
9.6
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. See "Watchdog Timer" on page 51 for details on operation of the Watchdog Timer. Figure 9-6.
CC
Watchdog Reset During Operation
CK
9.7
Internal Voltage Reference
ATTINY43U features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.
9.7.1
Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 20-4 on page 158. To save power, the reference is not always turned on. The reference is on during the following situations: 1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse). 2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR). 3. When the ADC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.
9.8
Watchdog Timer
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 9-3 on page 56. The WDR - Watchdog Reset - instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different
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clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATTINY43U resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 9-3 on page 56. The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can be very helpful when using the Watchdog to wake-up from Power-down. To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 9-1. See "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 52 for details. Table 9-1.
WDTON Unprogrammed Programmed
WDT Configuration as a Function of the Fuse Settings of WDTON
Safety Level 1 2 WDT Initial State Disabled Enabled How to Disable the WDT Timed sequence Always enabled How to Change Timeout No limitations Timed sequence
Figure 9-7.
Watchdog Timer
128 kHz OSCILLATOR OSC/2K OSC/4K OSC/8K
WATCHDOG PRESCALER OSC/1024K OSC/256K OSC/128K OSC/512K OSC/16K OSC/32K OSC/64K
WATCHDOG RESET WDP0 WDP1 WDP2 WDP3 WDE
MCU RESET
9.8.1
Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to one without any restriction. A timed sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared.
9.8.1.1
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9.8.1.2
Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: 1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.
9.8.2
Code Example The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example(1)
WDT_off: wdr ; Clear WDRF in MCUSR ldi out r16, (0<; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent unintentional Watchdog Reset in r16, WDTCR ori r16, (1<C Code Example(1)
void WDT_off(void) { _WDR(); /* Clear WDRF in MCUSR */ MCUSR = 0x00 /* Write logical one to WDCE and WDE */ WDTCR |= (1<53
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9.9
9.9.1
Register Description
MCUSR - MCU Status Register The MCU Status Register provides information on which reset source caused an MCU Reset.
Bit 0x34 (0x54) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUSR
See Bit Description
* Bits 7:4 - Res: Reserved Bits These bits are reserved and will always read zero. * Bit 3 - WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 2 - BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 1 - EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. * Bit 0 - PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. 9.9.2 WDTCSR - Watchdog Timer Control and Status Register
Bit 0x21 (0x41) Read/Write Initial Value 7 WDIF R/W 0 6 WDIE R/W 0 5 WDP3 R/W 0 4 WDCE R/W 0 3 WDE R/W X 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCSR
* Bit 7 - WDIF: Watchdog Timeout Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed. * Bit 6 - WDIE: Watchdog Timeout Interrupt Enable When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed instead of a reset if a timeout in the Watchdog Timer occurs. If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared,
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the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 9-2.
WDE 0 0 1 1
Watchdog Timer Configuration
WDIE 0 1 0 1 Watchdog Timer State Stopped Running Running Running Action on Time-out None Interrupt Reset Interrupt
* Bit 4 - WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. See the description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 52. * Bit 3 - WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See "Timed Sequences for Changing the Configuration of the Watchdog Timer" on page 52. In safety level 1, WDE is overridden by WDRF in MCUSR. See "MCUSR - MCU Status Register" on page 54 for description of WDRF. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.
Note: If the watchdog timer is not going to be used in the application, it is important to go through a watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which in turn will lead to a new watchdog reset. To avoid this situation, the application software should always clear the WDRF flag and the WDE control bit in the initialization routine.
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* Bits 5, 2:0 - WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1, and 0 The WDP[3:0] bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 9-3 on page 56. Table 9-3.
WDP3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Watchdog Timer Prescale Select
WDP2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 0 1 0 1 0 Reserved 1 0 1 Number of WDT Oscillator Cycles 2K cycles 4K cycles 8K cycles 16K cycles 32K cycles 64K cycles 128K cycles 256K cycles 512K cycles 1024K cycles Typical Time-out at VCC = 5.0V 16 ms 32 ms 64 ms 0.125 s 0.25 s 0.5 s 1.0 s 2.0 s 4.0 s 8.0 s
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10. Interrupts
This section describes the specifics of the interrupt handling as performed in ATTINY43U. For a general explanation of the AVR interrupt handling, see "Reset and Interrupt Handling" on page 13.
10.1
Interrupt Vectors
Table 10-1.
Vector No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Reset and Interrupt Vectors
Program Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F Source RESET INT0 PCINT0 PCINT1 WDT TIMER1_COMPA TIMER1_COMPB TIMER1_OVF TIMER0_COMPA TIMER0_COMPB TIMER0_OVF ANA_COMP ADC EE_RDY USI_START USI_OVF Interrupt Definition External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset External Interrupt Request 0 Pin Change Interrupt Request 0 Pin Change Interrupt Request 1 Watchdog Time-out Timer/Counter1 Compare Match A Timer/Counter1 Compare Match B Timer/Counter1 Overflow Timer/Counter0 Compare Match A Timer/Counter0 Compare Match B Timer/Counter0 Overflow Analog Comparator ADC Conversion Complete EEPROM Ready USI Start USI Overflow
If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATTINY43U is:
Address Labels Code 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp RESET INT0 PCINT0 PCINT1 WDT TIM1_COMPA TIM1_COMPB TIM1_OVF
Comments ; Reset Handler ; IRQ0 Handler ; PCINT0 Handler ; PCINT1 Handler ; Watchdog Interrupt Handler ; Timer1 Compare A Handler ; Timer1 Compare B Handler ; Timer1 Overflow Handler
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0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F ; 0x0010 0x0011 0x0012 0x0013 ... ...
rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp RESET: ldi out sei
TIM0_COMPA TIM0_COMPB TIM0_OVF ANA_COMP ADC EE_RDY USI_STR USI_OVF
; Timer0 Compare A Handler ; Timer0 Compare B Handler ; Timer0 Overflow Handler ; Analog Comparator Handler ; ADC Conversion Handler ; EEPROM Ready Handler ; USI Start Handler ; USI Overflow Handler
r16, low(RAMEND); Main program start SPL,r16 xxx ... ; Set Stack Pointer to top of RAM ; Enable interrupts
...
10.2
External Interrupts
The External Interrupts are triggered by the INT0 pin or any of the PCINT pins. Observe that, if enabled, the interrupts will trigger even if INT0 or the PCINT pins are configured as outputs. This feature provides a way of generating a software interrupt, as follows. * Pin Change Interrupt PCI0 triggers if a pin in PCINT7:0 is toggled while enabled * Pin Change Interrupt PCI1 triggers if a pin in PCINT15:8 is toggled while enabled
The PCMSK0 and PCMSK1 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT15..0 are detected asynchronously. This means that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The INT0 interrupt can be triggered by a falling or rising edge, or a low level. This is configured as described in "MCUCR - MCU Control Register" on page 59. When the INT0 interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Low level and edge interrupts on INT0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated and execution will continue from the instruction following the SLEEP command. The start-up time is defined by the SUT and CKSEL fuses, as described in "System Clock and Clock Options" on page 23. 10.2.1 Pin Change Interrupt Timing An example of timing of a pin change interrupt is shown in Figure 10-1 below.
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Figure 10-1. Timing of pin change interrupts
PCINT(0)
LE
pin_lat
D
Q
pcint_in_(0) pin_sync PCINT(0) in PCMSK(x)
0 x clk
pcint_syn
pcint_setflag PCIF
clk
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
10.3
10.3.1
Register Description
MCUCR - MCU Control Register The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit 0x35 (0x55) Read/Write Initial Value 7 BODS R/W 0 6 PUD R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 BODSE R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR
* Bits 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 External Interrupt 0 is activated by the external pin INT0 if the I-flag of SREG and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 10-2 on page 60. Edges on INT0 are registered asynchronously. Pulses on INT0 wider than the pulse width given in Table 20-6 on page 158 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
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If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 10-2.
ISC01 0 0 1 1
Interrupt 0 Sense Control
ISC00 0 1 0 1 Description The low level of INT0 generates an interrupt request asynchronously Any logical change on INT0 generates an interrupt request asynchronously The falling edge of INT0 generates an interrupt request asynchronously The rising edge of INT0 generates an interrupt request asynchronously
10.3.2
GIMSK - General Interrupt Mask Register
Bit 0x3B (0x5B) Read/Write Initial Value 7 - R 0 6 INT0 R/W 0 5 PCIE1 R/W 0 4 PCIE0 R/W 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIMSK
* Bits 7, 3:0 - Res: Reserved Bits These bits are reserved and will always read zero. * Bit 6 - INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU Control Register (MCUCR) define whether the external interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. * Bit 5 - PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register. * Bit 4 - PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register. 10.3.3 GIFR - General Interrupt Flag Register
Bit 0x3A (0x5A) Read/Write Initial Value 7 - R 0 6 INTF0 R/W 0 5 PCIF1 R/W 0 4 PCIF0 R/W 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 GIFR
* Bits 7, 3:0 - Res: Reserved Bits These bits are reserved and will always read zero.
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* Bit 6 - INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT0 is configured as a level interrupt. * Bit 5 - PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. * Bit 4 - PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. 10.3.4 PCMSK1 - Pin Change Mask Register 1
Bit 0x20 (0x40) Read/Write Initial Value 7 PCINT15 R/W 0 6 PCINT14 R/W 0 5 PCINT13 R/W 0 4 PCINT12 R/W 0 3 PCINT11 R/W 0 2 PCINT10 R/W 0 1 PCINT9 R/W 0 0 PCINT8 R/W 0 PCMSK1
* Bits 7:0 - PCINT[15:8]: Pin Change Enable Mask 15:8 Each PCINT15:8 bit selects whether pin change interrupt is enabled on the corresponding I/O pin, or not. If PCINT15:8 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 10.3.5 PCMSK0 - Pin Change Mask Register 0
Bit 0x12 (0x32) Read/Write Initial Value 7 PCINT7 R 0 6 PCINT6 R/W 0 5 PCINT5 R/W 0 4 PCINT4 R/W 0 3 PCINT3 R/W 0 2 PCINT2 R/W 0 1 PCINT1 R/W 0 0 PCINT0 R/W 0 PCMSK0
* Bits 7:0 - PCINT[7:0]: Pin Change Enable Mask 7:0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.
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11. I/O Ports
11.1 Introduction
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 11-1 on page 62. See "Electrical Characteristics" on page 155 for a complete list of parameters. Figure 11-1. I/O Pin Equivalent Schematic
Rpu
Pxn
Logic Cpin
See Figure "General Digital I/O" for Details
All registers and bit references in this section are written in general form. A lower case "x" represents the numbering letter for the port, and a lower case "n" represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. Three I/O memory address locations are allocated for each port, one each for the Data Register - PORTx, Data Direction Register - DDRx, and the Port Input Pins - PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable - PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in "Ports as General Digital I/O" on page 63. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in "Alternate Port Functions" on page 67. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.
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11.2
Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 11-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 11-2. General Digital I/O(1)
PUD
Q
D
DDxn Q CLR
RESET
WDx RDx
1 Pxn
Q D PORTxn Q CLR
0
RESET WRx SLEEP RRx
WPx
SYNCHRONIZER
D Q D Q
RPx
PINxn L Q Q
clk I/O
PUD: SLEEP: clkI/O:
PULLUP DISABLE SLEEP CONTROL I/O CLOCK
WDx: RDx: WRx: RRx: RPx: WPx:
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER
Note:
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports.
11.2.1
Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. The DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
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63
be configured as an output pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running. If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 11.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b10) as an intermediate step. Table 11-1 on page 64 summarizes the control signals for the pin value. Table 11-1.
DDxn 0 0 0 1 1
11.2.3
Port Pin Configurations
PUD (in MCUCR) X 0 1 X X I/O Input Input Input Output Output Pull-up No Yes No No No Comment Tri-state (Hi-Z) Pxn will source current if ext. pulled low. Tri-state (Hi-Z) Output Low (Sink) Output High (Source)
PORTxn 0 1 1 0 1
11.2.4
Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 11-2 on page 63, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 11-3 on page 65 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively.
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Figure 11-3. Synchronization when Reading an Externally Applied Pin value
SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd, max t pd, min 0xFF XXX XXX in r17, PINx
Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the "SYNC LATCH" signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between 1/2 and 11/2 system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 11-4 on page 65. The out instruction sets the "SYNC LATCH" signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is one system clock period. Figure 11-4. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd 0xFF out PORTx, r16 nop 0xFF
in r17, PINx
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The following code example shows how to set port A pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1)
... ; Define pull-ups and set outputs high ; Define directions for port pins ldi ldi out out nop ; Read port pins in ... r16,PINA r16,(1<; Insert nop for synchronization
C Code Example
unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTA = (1<11.2.5
Digital Input Enable and Sleep Modes As shown in Figure 11-2 on page 63, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to VCC/2. SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in "Alternate Port Functions" on page 67. If a logic high level ("one") is present on an asynchronous external interrupt pin configured as "Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin" while the external interrupt
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is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change. 11.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pulldown. Connecting unused pins directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output.
11.3
Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure 11-5 on page 68 shows how the port pin control signals from the simplified Figure 11-2 on page 63 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.
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Figure 11-5. Alternate Port Functions(1)
PUOExn PUOVxn
1 0
PUD
DDOExn DDOVxn
1 0
QD DDxn Q CLR
PVOExn PVOVxn
WDx RESET RDx
1 Pxn 0
Q D
1 0
PORTxn
PTOExn WPx
DIEOExn DIEOVxn
1 0
Q CLR
RESET RRx
WRx
SLEEP SYNCHRONIZER
D
SET
RPx
Q
D
Q
PINxn L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PTOExn:
Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL Pxn, PORT TOGGLE OVERRIDE ENABLE
PUD: WDx: RDx: RRx: WRx: RPx: WPx: clkI/O: DIxn: AIOxn:
PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN WRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx
Note:
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
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Table 11-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 11-5 on page 68 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. Table 11-2.
Signal Name PUOE
Generic Description of Overriding Signals for Alternate Functions
Full Name Pull-up Override Enable Pull-up Override Value Data Direction Override Enable Data Direction Override Value Description If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits. If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit. If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit. If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit. If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit. If PTOE is set, the PORTxn Register bit is inverted. If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode). If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode). This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt-trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/Output to/from alternate functions. The signal is connected directly to the pad, and can be used bidirectionally.
PUOV
DDOE
DDOV
PVOE
Port Value Override Enable Port Value Override Value Port Toggle Override Enable Digital Input Enable Override Enable Digital Input Enable Override Value
PVOV PTOE
DIEOE
DIEOV
DI
Digital Input
AIO
Analog Input/Output
The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.
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11.3.1
Alternate Functions of Port A The Port A pins with alternate function are shown in Table 11-3 on page 70. Table 11-3. Port A Pins Alternate Functions
Alternate Function ADC0: ADC input channel 0. PCINT0:Pin change interrupt 0 source 0. ADC1: ADC input channel 1. PCINT1:Pin change interrupt 0 source 1. ADC2: ADC input channel 2. PCINT2: Pin change interrupt 0 source 2. ADC3: ADC input channel 3. PCINT3: Pin change interrupt 0 source 3. AIN0: Analog Comparator Positive Input. PCINT4: Pin change interrupt 0 source 4. AIN1: Analog Comparator Negative Input. PCINT5: Pin change interrupt 0 source 5. PCINT6: Pin change interrupt 0 source 6. CLKI: External Clock Input. RESET: Reset pin. dW: debugWire I/O. PCINT7: Pin change interrupt 0 source 7
Port Pin PA0 PA1 PA2 PA3 PA4 PA5 PA6
PA7
* Port A, Bit 0 - ADC0/PCINT0 ADC0: Analog to Digital Converter, Channel 0. PCINT0: Pin Change Interrupt source 0. The PA0 pin can serve as an external interrupt source for pin change interrupt 0. * Port A, Bit 1 - ADC1/PCINT1 ADC1: Analog to Digital Converter, Channel 1. PCINT1: Pin Change Interrupt source 1. The PA1 pin can serve as an external interrupt source for pin change interrupt 0. * Port A, Bit 2 - ADC2/PCINT2 ADC2: Analog to Digital Converter, Channel 2. PCINT2: Pin Change Interrupt source 2. The PA2 pin can serve as an external interrupt source for pin change interrupt 0. * Port A, Bit 3 - ADC3/PCINT3 ADC3: Analog to Digital Converter, Channel 3. PCINT3: Pin Change Interrupt source 3. The PA3 pin can serve as an external interrupt source for pin change interrupt 0.
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* Port A, Bit 4 - AIN0/PCINT4 AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCINT4: Pin Change Interrupt source 4. The PA4 pin can serve as an external interrupt source for pin change interrupt 0. * Port A, Bit 5 - AIN1/PCINT5 AIN1: Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCINT5: Pin Change Interrupt source 5. The PA5 pin can serve as an external interrupt source for pin change interrupt 0. * Port A, Bit 6 - CLKI/PCINT6 CLKI: External Clock Input. When used as a clock pin, the pin can not be used as an I/O pin. PCINT6: Pin Change Interrupt source 6. The PA6 pin can serve as an external interrupt source for pin change interrupt 0. * Port A, Bit 7 - RESET/dW/PCINT7 RESET: External Reset input is active low and enabled by unprogramming ("1") the RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. PCINT7: Pin Change Interrupt source 7. The PA7 pin can serve as an external interrupt source for pin change interrupt 0.
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Table 11-4 on page 72 to Table 11-6 on page 73 relate the alternate functions of Port A to the overriding signals shown in Figure 11-5 on page 68. Table 11-4.
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE
Overriding Signals for Alternate Functions in PA7..PA6
PA7/RESET/dW/PCINT7 RSTDISBL 1 RSTDISBL(1) + MONCOM_ENABLE MONCOM_ENABLE * debugWire Transmit RSTDISBL(1) + MONCOM_ENABLE 0 0 RSTDISBL(1) + MONCOM_ENABLE + PCINT7 * PCIE0 MONCOM_ENABLE + MONCOM_ENABLE * RSTDISBL(1) * PCINT7 * PCIE0) dW/PCINT7 Input
(1)
PA6/ PCINT6 EXT_CLK (2) 0 EXT_CLK(2) 0 EXT_CLK(2) 0 0 EXT_CLK(2) + (PCINT6 * PCIE0) (EXT_CLK(2) * PWR_DOWN) + (EXT_CLK(2) * PCINT7 * PCIE0) CLKI/PCINT6 Input
+ MONCOM_ENABLE
DIEOV DI AIO 1. 2.
RSTDISBL is 1 when the Fuse is "0" (Programmed). EXT_CLOCK = external clock is selected as system clock
Table 11-5.
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO
Overriding Signals for Alternate Functions in PA5..PA4
PA5/AIN1/ PCINT5 0 0 0 0 0 0 0 (PCINT5 * PCIE) + AIN1D PCINT5 * PCIE0 PCINT5 Input Analog Comparator Negative Input
PA4/AIN0/PCINT4 0 0 0 0 0 0 0 (PCINT4 * PCIE0) + AIN0D PCINT4 * PCIE0 PCINT4 input Analog Comparator Positive Input
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Table 11-6.
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO
Overriding Signals for Alternate Functions in PA3..PA2
PA3/ADC3/PCINT3 0 0 0 0 0 0 0 (PCINT3 * PCIE0) + ADC3D PCINT3 * PCIE0 PCINT3 Input ADC3 Input 0 0 (PCINT2 * PCIE) + ADC2D PCINT2 * PCIE0 PCINT2 Input ADC2 0 0 PA2/ADC2/PCINT2
Table 11-7.
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO
Overriding Signals for Alternate Functions in PA1..PA0
PA1/ADC1/PCINT1 0 0 0 0 0 0 0 (PCINT1 * PCIE) + ADC1D PCINT1 * PCIE0 PCINT1 Input ADC1 Input
PA0/ADC0/PCINT0
0
0
0 0 (PCINT0 * PCIE0) + ADC0D PCINT0 * PCIE0 PCINT0 Input ADC0 Input
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11.3.2
Alternate Functions of Port B The Port B pins with alternate function are shown in Table 11-8 on page 74. Table 11-8. Port B Pins Alternate Functions
Alternate Function T0: Timer/Counter0 Counter Source. PCINT8: Pin change interrupt 1 source 8. OC0A: Timer/Counter0 Compare Match A output. PCINT9: Pin change interrupt 1 source 9. OC0B: Timer/Counter0 Compare Match B output. PCINT10:Pin change interrupt 1 source 10. T1: Timer/Counter1 Counter Source. CLKO: System Clock Output. PCINT11:Pin change interrupt 1 source 11. OC1A: Timer/Counter1 Compare Match A output. DI: USI Data Input three wire mode. SDA: USI Data Input two wire mode. PCINT12:Pin change interrupt 1 source 12. OC1B: Timer/Counter1 Compare Match B output. DO: USI Data Output three wire mode. PCINT13:Pin change interrupt 1 source 13. USCK: USI Clock three wire mode. SCL: USI Clock two wire mode. PCINT14:Pin change interrupt 1 source 14. INT0: External Interrupt 0 input. PCINT15:Pin change interrupt 1 source 15.
Port Pin PB0 PB1 PB2
PB3
PB4
PB5
PB6
PB7
* Port B, Bit 0 - T0/PCINT8 T0: Timer/Counter0 Counter Source. PCINT8: Pin Change Interrupt source 8. The PB0 pin can serve as an external interrupt source for pin change interrupt 1. * Port B, Bit 1 - OC0A/PCINT9 OC0A: Output Compare Match output: The PB1 pin can serve as an external output for the Timer/Counter0 Compare Match A. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function. PCINT9: Pin Change Interrupt source 9. The PB1 pin can serve as an external interrupt source for pin change interrupt 1. * Port B, Bit 2 - OC0B/PCINT10 OC0B: Output Compare Match output: The PB2 pin can serve as an external output for the Timer/Counter0 Compare Match A. The PB2 pin has to be configured as an output (DDB2 set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function.
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PCINT10: Pin Change Interrupt source 10. The PB2 pin can serve as an external interrupt source for pin change interrupt 1. * Port B, Bit 3 - T1/CLKO/PCINT11 T1: Timer/Counter1 Counter source. CLKO: System Clock Output. The system clock can be output on the PB3 pin. The system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB3 and DDB3 settings. It will also be output during reset. PCINT11: Pin Change Interrupt source 11. The PB3 pin can serve as an external interrupt source for pin change interrupt 1. * Port B, Bit 4 - DI/SDA/OC1A/PCINT12 DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port functions, so pin must be configure as an input for DI function. SDA: Two-wire mode Serial Interface Data. OC1A, Output Compare Match output: The PB4 pin can serve as an external output for the Timer/Counter1 Compare Match A. The PB4 pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. PCINT12: Pin Change Interrupt source 12. The PB4 pin can serve as an external interrupt source for pin change interrupt 1. * Port B, Bit 5 - DO/OC1B/PCINT13 DO: Data Output in USI Three-wire mode. Data output (DO) overrides PORTB5 value and it is driven to the port when the data direction bit DDB5 is set (one). However the PORTB5 bit still controls the pullup, enabling pullup if direction is input and PORTB5 is set (one). OC1B: Output Compare Match output: The PB5 pin can serve as an external output for the Timer/Counter1 Compare Match B. The PB5 pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. PCINT13: Pin Change Interrupt source 13. The PB5 pin can serve as an external interrupt source for pin change interrupt 1. * Port B, Bit 6 - USCK/SCL/PCINT14 USCK: Three-wire mode Universal Serial Interface Clock. SCL: Two-wire mode Serial Clock for USI Two-wire mode. PCINT14: Pin Change Interrupt source 14. The PB6 pin can serve as an external interrupt source for pin change interrupt 1. * Port B, Bit 7 - INT0/PCINT15 INT0: External Interrupt Request 0. PCINT15: Pin Change Interrupt source 15. The PB7 pin can serve as an external interrupt source for pin change interrupt 1.
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Table 11-9 on page 76 to Table 11-12 on page 77 relate the alternate functions of Port B to the overriding signals shown in Figure 11-5 on page 68. Table 11-9.
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO
Overriding Signals for Alternate Functions in PB7..PB6
PB7/INT0/PCINT15 0 0 0 0 0 0 0 (PCINT15 * PCIE1) + INT0 (PCINT15 * PCIE1) + INT0 INT0/PCINT15 PB6/PCINT14 0 0 USIWM1 USI_SCL_HOLD + PORTB6 USIWM1 0 USIPTOE (PCINT14 * PCIE1) + USISIE (PCINT14 * PCIE1) + USISIE PCINT14/USCK/SCL
Table 11-10. Overriding Signals for Alternate Functions in PB5..PB4
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PB5/OC1B/PCINT13 0 0 0 0 OC1B Enable + (USIWM1 * USIWM0) OC1B * (~USIWM1* USIWM0) + USIWM1 * USIWM0 * DO 0 PCINT13 * PCIE1 PCINT13 * PCIE1 PCINT13 PB4/OC1A/PCINT10 0 0 USIWM1 (SDA + PORTB4) * DDRB4 OC1A Enable + (USIWM1 * DDRB4) OC1A * (USIWM1* DDRB4) 0 PCINT10 * PCIE1 + USISIE PCINT10 * PCIE1 + USISIE PCINT10/DI/SDA
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Table 11-11. Overriding Signals for Alternate Functions in PB3..PB2
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PB3/T1/CLKO/PCINT9 CKOUT 0 CKOUT 1'b1 CKOUT CKOUT * System Clock 0 PCINT9 * PCIE1 PCINT9 * PCIE1 T1/PCINT9 Input PB2/OC0B/PCINT8 0 0 0 0 OC0B Enable OC0B 0 PCINT8 * PCIE1 PCINT8 * PCIE1 PCINT8 Input
Table 11-12. Overriding Signals for Alternate Functions in PB1..PB0
Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PB1/OC0A/PCINT7 0 0 0 0 0 OC0A Enable OC0A PCINT7 * PCIE1 PCINT7 * PCIE1 PCINT7 Input PB0/T0/PCINT6 0 0 0 0 0 0 0 PCINT6 * PCIE1 PCINT6 * PCIE1 PCINT6 Input
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11.4
11.4.1
Register Description
MCUCR - MCU Control Register
Bit 0x35 (0x55) Read/Write Initial Value 7 BODS R/W 0 6 PUD R/W 0 5 SE R/W 0 4 SM1 R/W 0 3 SM0 R/W 0 2 BODSE R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR
* Bit 6 - PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See "Configuring the Pin" on page 63 for more details about this feature.
11.4.2
PORTA - Port A Data Register
Bit 0x1B (0x3B) Read/Write Initial Value 7
PORTA7
6
PORTA6
5
PORTA5
4
PORTA4
3
PORTA3
2
PORTA2
1
PORTA1
0
PORTA0 PORTA
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
11.4.3
DDRA - Port A Data Direction Register
Bit 0x1A (0x3A) Read/Write Initial Value 7 DDA7 R/W 0 6 DDA6 R/W 0 5 DDA5 R/W 0 4 DDA4 R/W 0 3 DDA3 R/W 0 2 DDA2 R/W 0 1 DDA1 R/W 0 0 DDA0 R/W 0 DDRA
11.4.4
PINA - Port A Input Pins Address
Bit 0x19 (0x39) Read/Write Initial Value 7 PINA7 R/W N/A 6 PINA6 R/W N/A 5 PINA5 R/W N/A 4 PINA4 R/W N/A 3 PINA3 R/W N/A 2 PINA2 R/W N/A 1 PINA1 R/W N/A 0 PINA0 R/W N/A PINA
11.4.5
PORTB - Port B Data Register
Bit 0x18 (0x38) Read/Write Initial Value 7
PORTB7
6
PORTB6
5
PORTB5
4
PORTB4
3
PORTB3
2
PORTB2
1
PORTB1
0
PORTB0 PORTB
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
11.4.6
DDRB - Port B Data Direction Register
Bit 0x17 (0x37) Read/Write Initial Value 7 DDB7 R/W 0 6 DDB6 R/W 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB
11.4.7
PINB - Port BInput Pins Address
Bit 0x16 (0x36) Read/Write Initial Value 7 PINB7 R/W N/A 6 PINB6 R/W N/A 5 PINB5 R/W N/A 4 PINB4 R/W N/A 3 PINB3 R/W N/A 2 PINB2 R/W N/A 1 PINB1 R/W N/A 0 PINB0 R/W N/A PINB
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12. 8-bit Timer/Counter with PWM (Timer/Counter0 and Timer/Counter1)
12.1 Features
* * * * * * *
Two Independent Output Compare Units Double Buffered Output Compare Registers Clear Timer on Compare Match (Auto Reload) Glitch Free, Phase Correct Pulse Width Modulator (PWM) Variable PWM Period Frequency Generator Six Independent Interrupt Sources (TOV0, OCF0A, OCF0B, TOV1, OCF1A, and OCF1B)
12.2
Overview
Timer/Counter0 and Timer/Conter1 are general purpose Timer/Counter modules with two independent Output Compare Units, each, and with PWM support. They allow accurate program execution timing (event management) and wave generation. Register and bit references in this section are written in general form. A lower case "n" replaces the Timer/Counter number, and a lower case "x" replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 12-1 on page 79. For the actual placement of I/O pins, refer to Figure 1-1 on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "Register Description" on page 90. Figure 12-1. 8-bit Timer/Counter Block Diagram
Count Clear Direction Control Logic TOVn (Int.Req.) clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn
=
=0
OCnA (Int.Req.)
=
OCRnA Fixed TOP Value
Waveform Generation
OCnA
DATA BUS
OCnB (Int.Req.) Waveform Generation OCnB
=
OCRnB
TCCRnA
TCCRnB
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12.2.1
Registers The Timer/Counter (TCNTn) and Output Compare Registers (OCRnA and OCRnB) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkTn). The double buffered Output Compare Registers (OCRnA and OCRnB) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OCnA and OCnB). See "Output Compare Unit" on page 81 for details. The Compare Match event will also set the Compare Flag (OCFnA or OCFnB) which can be used to generate an Output Compare interrupt request.
12.2.2
Definitions The definitions in Table 12-1 are used extensively throughout the document. Table 12-1. BOTTOM MAX TOP Definitions The counter reaches the BOTTOM when it becomes 0x00. The counter reaches its MAXimum when it becomes 0xFF (decimal 255). The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCRnA Register. The assignment is dependent on the mode of operation.
12.3
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter Control Register (TCCRnB). For details on clock sources and prescaler, see "Timer/Counter Prescaler" on page 98.
12.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 12-2 on page 81 shows a block diagram of the counter and its surroundings.
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Figure 12-2. Counter Unit Block Diagram
DATA BUS
TOVn (Int.Req.)
Clock Select count TCNTn clear direction ( From Prescaler ) bottom top Control Logic clkTn Edge Detector Tn
Signal description (internal signals): count direction clear clkTn top bottom Increment or decrement TCNTn by 1. Select between increment and decrement. Clear TCNTn (set all bits to zero). Timer/Counter clock, referred to as clkTn in the following. Signalize that TCNTn has reached maximum value. Signalize that TCNTn has reached minimum value (zero).
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkTn). clkTn can be generated from an external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be accessed by the CPU, regardless of whether clkTn is present or not. A CPU write overrides (has priority over) all counter clear or count operations. The counting sequence is determined by the setting of the WGMn1 and WGMn0 bits located in the Timer/Counter Control Register (TCCRnA) and the WGMn2 bit located in the Timer/Counter Control Register B (TCCRnB). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OCnA. For more details about advanced counting sequences and waveform generation, see "Modes of Operation" on page 84. The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn1:0 bits. TOVn can be used for generating a CPU interrupt.
12.5
Output Compare Unit
The 8-bit comparator continuously compares TCNTn with the Output Compare Registers (OCRnA and OCRnB). Whenever TCNTn equals OCRnA or OCRnB, the comparator signals a match. A match will set the Output Compare Flag (OCFnA or OCFnB) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGMn2:0 bits and Compare Output mode (COMnx1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation. See "Modes of Operation" on page 84. Figure 12-3 on page 82 shows a block diagram of the Output Compare unit. 81
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Figure 12-3. Output Compare Unit, Block Diagram
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top bottom FOCn
Waveform Generator
OCnx
WGMn1:0
COMnx1:0
The OCRnx Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is disabled the CPU will access the OCRnx directly. 12.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (nx) bit. Forcing Compare Match will not set the OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real Compare Match had occurred (the COMnx1:0 bits settings define whether the OCnx pin is set, cleared or toggled). Compare Match Blocking by TCNTn Write All CPU write operations to the TCNTn Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. Using the Output Compare Unit Since writing TCNTn in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNTn when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNTn equals the OCRnx value, the Compare Match will be missed, resulting in incorrect waveform
12.5.2
12.5.3
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generation. Similarly, do not write the TCNTn value equal to BOTTOM when the counter is down-counting. The setup of the OCnx should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OCnx value is to use the Force Output Compare (nx) strobe bits in Normal mode. The OCnx Registers keep their values even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately.
12.6
Compare Match Output Unit
The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next Compare Match. Also, the COMnx1:0 bits control the OCnx pin output source. Figure 12-4 on page 83 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset occur, the OCnx Register is reset to "0". Figure 12-4. Compare Match Output Unit, Schematic (non-PWM Mode)
COMnx1 COMnx0 FOCn
Waveform Generator
D
Q
1 OCn Pin
OCnx D
DATA BUS
0
Q
PORT D Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visible on the pin. The port override function is independent of the Waveform Generation mode. 83
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The design of the Output Compare pin logic allows initialization of the OCnx state before the output is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation, see "Register Description" on page 90 12.6.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the OCnx Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 12-2 on page 90. For fast PWM mode, refer to Table 12-3 on page 91, and for phase correct PWM refer to Table 12-4 on page 91. A change of the COMnx1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits.
12.7
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn2:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (See "Modes of Operation" on page 84). For detailed timing information refer to Figure 12-8 on page 89, Figure 12-9 on page 89, Figure 12-10 on page 89 and Figure 12-11 on page 90 in "Timer/Counter Timing Diagrams" on page 88.
12.7.1
Normal Mode The simplest mode of operation is the Normal mode (WGMn2:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOVn Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.
12.7.2
Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGMn2:0 = 2), the OCRnA Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNTn) matches the OCRnA. The OCRnA defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events.
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The timing diagram for the CTC mode is shown in Figure 12-5 on page 85. The counter value (TCNTn) increases until a Compare Match occurs between TCNTn and OCRnA, and then counter (TCNTn) is cleared. Figure 12-5. CTC Mode, Timing Diagram
OCnx Interrupt Flag Set
TCNTn
OCn (Toggle) Period
1 2 3 4
(COMnx1:0 = 1)
An interrupt can be generated each time the counter value reaches the TOP value by using the OCFnA Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCRnA is lower than the current value of TCNTn, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can occur. For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOCnx = fclk_I/O/2 when OCRnA is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCnx = ------------------------------------------------2 N ( 1 + OCRnx ) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 12.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGMn2:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGMn2:0 = 3, and OCRnA when WGMn2:0 = 7. In noninverting Compare Output mode, the Output Compare (OCnx) is cleared on the Compare Match between TCNTn and OCRnx, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited
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for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 12-6 on page 86. The TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent Compare Matches between OCRnx and TCNTn. Figure 12-6. Fast PWM Mode, Timing Diagram
OCRnx Interrupt Flag Set
OCRnx Update and TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three: Setting the COMnA1:0 bits to one allowes the OCnA pin to toggle on Compare Matches if the WGMn2 bit is set. This option is not available for the OCnB pin (See Table 12-3 on page 91). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnxPWM = ----------------N 256 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCRnA Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnA is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCRnA equal to MAX will result
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in a constantly high or low output (depending on the polarity of the output set by the COMnA1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OCnx to toggle its logical level on each Compare Match (COMnx1:0 = 1). The waveform generated will have a maximum frequency of fOCnx = fclk_I/O/2 when OCRnA is set to zero. This feature is similar to the OCnA toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. 12.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGMn2:0 = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOTTOM. TOP is defined as 0xFF when WGMn2:0 = 1, and OCRnA when WGMn2:0 = 5. In noninverting Compare Output mode, the Output Compare (OCnx) is cleared on the Compare Match between TCNTn and OCRnx while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. In phase correct PWM mode the counter is incremented until the counter value matches TOP. When the counter reaches TOP, it changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 12-7 on page 87. The TCNTn value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent Compare Matches between OCRnx and TCNTn. Figure 12-7. Phase Correct PWM Mode, Timing Diagram
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
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The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COMnx1:0 to three: Setting the COMnA0 bits to one allows the OCnA pin to toggle on Compare Matches if the WGMn2 bit is set. This option is not available for the OCnB pin (See Table 12-4 on page 91). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OCnx Register at the Compare Match between OCRnx and TCNTn when the counter increments, and setting (or clearing) the OCnx Register at Compare Match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = ----------------N 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCRnA Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnA is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 12-7 on page 87 OCn has a transition from high to low even though there is no Compare Match. The point of this transition is to guaratee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. * OCRnA changes its value from MAX, like in Figure 12-7 on page 87. When the OCRnA value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. * The timer starts counting from a value higher than the one in OCRnA, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up.
12.8
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkTn) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set. Figure 12-8 on page 89 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.
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Figure 12-8. Timer/Counter Timing Diagram, no Prescaling
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 12-9 on page 89 shows the same timing data, but with the prescaler enabled. Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 12-10 on page 89 shows the setting of OCFnB in all modes and OCFnA in all modes except CTC mode and PWM mode, where OCRnA is TOP. Figure 12-10. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 12-11 on page 90 shows the setting of OCFnA and the clearing of TCNTn in CTC mode and fast PWM mode where OCRnA is TOP.
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Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8)
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRnx
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFnx
12.9
12.9.1
Register Description
TCCR0A - Timer/Counter Control Register A
Bit 0x30 (0x50) Read/Write Initial Value 7
COM0A1
6
COM0A0
5
COM0B1
4
COM0B0
3
-
2
-
1
WGM01
0
WGM00 TCCR0A
R/W 0
R/W 0
R/W 0
R/W 0
R 0
R 0
R/W 0
R/W 0
12.9.2
TCCR1A - Timer/Counter Control Register A
Bit 0x2F (0x4F) Read/Write Initial Value 7
COM1A1
6
COM1A0
5
COM1B1
4
COM1B0
3
-
2
-
1
WGM11
0
WGM10 TCCR1A
R/W 0
R/W 0
R/W 0
R/W 0
R 0
R 0
R/W 0
R/W 0
* Bits 7:6 - COMnA[1:0]: Compare Match Output A Mode These bits control the Output Compare pin (OCnA) behavior. If one or both of the COMnA[1:0] bits are set, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnA pin must be set in order to enable the output driver. When OCnA is connected to the pin, the function of the COMnA[1:0] bits depends on the WGMn[2:0] bit setting. Table 12-2 on page 90 shows the COMnA[1:0] bit functionality when the WGMn[2:0] bits are set to a normal or CTC mode (non-PWM). Table 12-2.
COMnA1 0 0 1 1
Compare Output Mode, non-PWM Mode
COMnA0 0 1 0 1 Description Normal port operation, OCnA disconnected. Toggle OCnA on Compare Match Clear OCnA on Compare Match Set OCnA on Compare Match
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Table 12-3 on page 91 shows the COMnA[1:0] bit functionality when the WGMn[1:0] bits are set to fast PWM mode. Table 12-3.
COMnA1 0 0 1 1 Note:
Compare Output Mode, Fast PWM Mode(1)
COMnA0 0 1 0 1 Description Normal port operation, OCnA disconnected. WGMn2 = 0: Normal Port Operation, OCnA Disconnected. WGMn2 = 1: Toggle OCnA on Compare Match. Clear OCnA on Compare Match, set OCnA at TOP Set OCnA on Compare Match, clear OCnA at TOP
1. A special case occurs when OCRnA equals TOP and COMnA1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Fast PWM Mode" on page 85 for more details.
Table 12-4 on page 91 shows the COMnA[1:0] bit functionality when the WGMn[2:0] bits are set to phase correct PWM mode. Table 12-4.
COMnA1 0 0 1 1 Note:
Compare Output Mode, Phase Correct PWM Mode(1)
COMnA0 0 1 0 1 Description Normal port operation, OCnA disconnected. WGMn2 = 0: Normal Port Operation, OCnA Disconnected. WGMn2 = 1: Toggle OCnA on Compare Match. Clear OCnA on Compare Match when up-counting. Set OCnA on Compare Match when down-counting. Set OCnA on Compare Match when up-counting. Clear OCnA on Compare Match when down-counting.
1. A special case occurs when OCRnA equals TOP and COMnA1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM Mode" on page 87 for more details.
* Bits 5:4 - COMnB[1:0]: Compare Match Output B Mode These bits control the Output Compare pin (OCnB) behavior. If one or both of the COMnB1:0 bits are set, the OCnB output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OCnB pin must be set in order to enable the output driver. When OCnB is connected to the pin, the function of the COMnB[1:0] bits depends on the WGMn[2:0] bit setting. Table 12-5 on page 91 shows the COMnB[1:0] bit functionality when the WGMn[2:0] bits are set to a normal or CTC mode (non-PWM). Table 12-5.
COMnB1 0 0 1 1
Compare Output Mode, non-PWM Mode
COMnB0 0 1 0 1 Description Normal port operation, OCnB disconnected. Toggle OCnB on Compare Match Clear OCnB on Compare Match Set OCnB on Compare Match
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Table 12-6 on page 92 shows the COMnB[1:0] bit functionality when the WGMn[2:0] bits are set to fast PWM mode. Table 12-6.
COMnB1 0 0 1 1 Note:
Compare Output Mode, Fast PWM Mode(1)
COMnB0 0 1 0 1 Description Normal port operation, OCnB disconnected. Reserved Clear OCnB on Compare Match, set OC0B at TOP Set OCnB on Compare Match, clear OC0B at TOP
1. A special case occurs when OCRnB equals TOP and COMnB1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Fast PWM Mode" on page 85 for more details.
Table 12-7 shows the COMnB[1:0] bit functionality when the WGMn2:0 bits are set to phase correct PWM mode. Table 12-7.
COMnB1 0 0 1 1 Note:
Compare Output Mode, Phase Correct PWM Mode(1)
COMnB0 0 1 0 1 Description Normal port operation, OCnB disconnected. Reserved Clear OCnB on Compare Match when up-counting. Set OCnB on Compare Match when down-counting. Set OCnB on Compare Match when up-counting. Clear OCnB on Compare Match when down-counting.
1. A special case occurs when OCRnB equals TOP and COMnB1 is set. In this case, the Compare Match is ignored, but the set or clear is done at TOP. See "Phase Correct PWM Mode" on page 87 for more details.
* Bits 3, 2 - Res: Reserved Bits These bits are reserved and will always read zero. * Bits 1:0 - WGMn[1:0]: Waveform Generation Mode Combined with the WGMn2 bit found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 12-8 on page 93. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see "Modes of Operation" on page 84).
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Table 12-8.
Waveform Generation Mode Bit Description
Timer/Counter Mode of Operation Normal PWM, Phase Correct CTC Fast PWM Reserved PWM, Phase Correct Reserved Fast PWM Update of OCRx at Immediate TOP Immediate TOP - TOP - TOP TOV Flag Set on(1) MAX BOTTOM MAX MAX - BOTTOM - TOP
Mode 0 1 2 3 4 5 6 7 Note:
WGMn2 0 0 0 0 1 1 1 1
WGMn1 0 0 1 1 0 0 1 1
WGMn0 0 1 0 1 0 1 0 1
TOP 0xFF 0xFF OCRnA 0xFF - OCRnA - OCRnA
1. MAX = 0xFF, BOTTOM = 0x00
12.9.3
TCCR0B - Timer/Counter Control Register B
Bit 0x33 (0x53) Read/Write Initial Value 7
FOC0A
6
FOC0B
5
-
4
-
3
WGM02
2
CS02
1
CS01
0
CS00 TCCR0B
W 0
W 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
12.9.4
TCCR1B - Timer/Counter Control Register B
Bit 0x2E (0x4E) Read/Write Initial Value 7
FOC1A
6
FOC1B
5
-
4
-
3
WGM12
2
CS12
1
CS11
0
CS10 TCCR1B
W 0
W 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 7 - FOCnA: Force Output Compare A The FOCnA bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCRnB is written when operating in PWM mode. When writing a logical one to the FOCnA bit, an immediate Compare Match is forced on the Waveform Generation unit. The OCnA output is changed according to its COMnA1:0 bits setting. Note that the FOCnA bit is implemented as a strobe. Therefore it is the value present in the COMnA1:0 bits that determines the effect of the forced compare. A FOCnA strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCRnA as TOP. The FOCnA bit is always read as zero. * Bit 6 - FOCnB: Force Output Compare B The FOCnB bit is only active when the WGM bits specify a non-PWM mode. 93
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However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written when operating in PWM mode. When writing a logical one to the FOCnB bit, an immediate Compare Match is forced on the Waveform Generation unit. The OCnB output is changed according to its COMnB1:0 bits setting. Note that the FOCnB bit is implemented as a strobe. Therefore it is the value present in the COMnB1:0 bits that determines the effect of the forced compare. A FOCnB strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCRnB as TOP. The FOCnB bit is always read as zero. * Bits 5, 4 - Res: Reserved Bits These bits are reserved and will always read zero. * Bit 3 - WGMn2: Waveform Generation Mode See the description in the "Register Description" on page 90. * Bits 2:0 - CSn[2:0]: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 12-9.
CSn2 0 0 0 0 1 1 1 1
Clock Select Bit Description
CSn0 0 1 0 1 0 1 0 1 Description No clock source (Timer/Counter stopped) clkI/O/(No prescaling) clkI/O/8 (From prescaler) clkI/O/64 (From prescaler) clkI/O/256 (From prescaler) clkI/O/1024 (From prescaler) External clock source on Tn pin. Clock on falling edge. External clock source on Tn pin. Clock on rising edge.
CSn1 0 0 1 1 0 0 1 1
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 12.9.5 TCNT0 - Timer/Counter Register
Bit 0x32 (0x52) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 TCNT0 R/W 0 R/W 0 R/W 0 TCNT0[7:0] R/W 0 R/W 0
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12.9.6
TCNT1 - Timer/Counter Register
Bit 0x2D (0x4D) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 TCNT1 R/W 0 R/W 0 R/W 0 TCNT1[7:0] R/W 0 R/W 0
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNTn Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNTn) while the counter is running, introduces a risk of missing a Compare Match between TCNTn and the OCRnx Registers. 12.9.7 OCR0A - Output Compare Register A
Bit 0x36 (0x56) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 OCR0A R/W 0 R/W 0 R/W 0 OCR0A[7:0] R/W 0 R/W 0
12.9.8
OCR1A - Output Compare Register A
Bit 0x2C (0x4C) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 OCR1A R/W 0 R/W 0 R/W 0 OCR1A[7:0] R/W 0 R/W 0
The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OCnA pin. 12.9.9 OCR0B - Output Compare Register B
Bit 0x3C (0x5C) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 OCR0B R/W 0 R/W 0 R/W 0 OCR0B[7:0] R/W 0 R/W 0
12.9.10
OCR1B - Output Compare Register B
Bit 0x2B (0x4B) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 OCR1B R/W 0 R/W 0 R/W 0 OCR1B[7:0] R/W 0 R/W 0
The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OCnB pin. 12.9.11 TIMSK0 - Timer/Counter 0 Interrupt Mask Register
Bit 0x39 (0x59) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 OCIE0B R/W 0 1 OCIE0A R/W 0 0 TOIE0 R/W 0 TIMSK0
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12.9.12
TIMSK1 - Timer/Counter 1 Interrupt Mask Register
Bit 0x0C (0x2C) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 OCIE1B R/W 0 1 OCIE1A R/W 0 0 TOIE1 R/W 0 TIMSK1
* Bits 7:3 - Res: Reserved Bits These bits are reserved and will always read zero. * Bit 2 - OCIEnB: Timer/Countern Output Compare Match B Interrupt Enable When the OCIEnB bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Countern occurs, i.e., when the OCFnB bit is set in the Timer/Counter Interrupt Flag Register - TIFRn. * Bit 1 - OCIEnA: Timer/Countern Output Compare Match A Interrupt Enable When the OCIEnA bit is written to one, and the I-bit in the Status Register is set, the Timer/Countern Compare Match A interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Countern occurs, i.e., when the OCFnA bit is set in the Timer/Counter n Interrupt Flag Register - TIFRn. * Bit 0 - TOIEn: Timer/Countern Overflow Interrupt Enable When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the Timer/Countern Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Countern occurs, i.e., when the TOVn bit is set in the Timer/Counter n Interrupt Flag Register - TIFRn. 12.9.13 TIFR0 - Timer/Counter 0 Interrupt Flag Register
Bit 0x38 (0x58) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 OCF0B R/W 0 1 OCF0A R/W 0 0 TOV0 R/W 0 TIFR0
12.9.14
TIFR1 - Timer/Counter 1 Interrupt Flag Register
Bit 0x0B (0x2B) Read/Write Initial Value 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 OCF1B R/W 0 1 OCF1A R/W 0 0 TOV1 R/W 0 TIFR1
* Bits 7:3 - Res: Reserved Bits These bits are reserved and will always read zero. * Bit 2 - OCFnB: Output Compare Flag n B The OCFnB bit is set when a Compare Match occurs between the Timer/Countern and the data in OCRnB - Output Compare Registern B. OCFnB is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCFnB is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIEnB (Timer/Counter Compare B Match Interrupt Enable), and OCFnB are set, the Timer/Countern Compare Match Interrupt is executed.
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* Bit 1 - OCFnA: Output Compare Flag n A The OCFnA bit is set when a Compare Match occurs between the Timer/Countern and the data in OCRnA - Output Compare Registern A. OCFnA is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCFnA is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIEnA (Timer/Countern Compare Match Interrupt Enable), and OCFnA are set, the Timer/Countern Compare Match Interrupt is executed. * Bit 0 - TOVn: Timer/Countern Overflow Flag The bit TOVn is set when an overflow occurs in Timer/Countern. TOVn is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOVn is cleared by writing a logic one to the flag. When the SREG I-bit, TOIEn (Timer/Countern Overflow Interrupt Enable), and TOVn are set, the Timer/Countern Overflow interrupt is executed.
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13. Timer/Counter Prescaler
Timer/Counter0 and Timer/Counter1 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counters. Tn is used as a general name, n = 0, 1. The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024.
13.1
Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/CounterCounter, and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by the Timer/Counter's clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution.
13.2
External Clock Source
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 13-1 on page 98 shows a functional equivalent block diagram of the Tn synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the high period of the internal system clock. The edge detector generates one clkT0 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects. Figure 13-1. Tn Pin Sampling
Tn
D LE
Q
D
Q
D
Q
Tn_sync (To Clock Select Logic)
clk I/O
Synchronization Edge Detector
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated. Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
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tem clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 13-2. Prescaler for Timer/Countern
clk I/O
Clear
PSR10
Tn
Synchronization
0
CSn0 CSn1 CSn2
TIMER/COUNTERn CLOCK SOURCE
clkTn
Note:
1. The synchronization logic on the input pins (Tn) is shown in Figure 13-1 on page 98.
13.3
13.3.1
Register Description
GTCCR - General Timer/Counter Control Register
Bit 0x23 (0x43) Read/Write Initial Value 7 TSM R/W 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 PSR10 R/W 0 GTCCR
* Bit 7 - TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted. This ensures that the Timer/Counter is halted and can be configured without the risk of advancing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by hardware, and the Timer/Counter start counting. * Bit 0 - PSR10: Prescaler Reset Timer/Counter When this bit is one, the Timer/Counter prescaler will be reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set.
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14. USI - Universal Serial Interface
14.1 Features
* * * * * *
Two-wire Synchronous Data Transfer (Master or Slave) Three-wire Synchronous Data Transfer (Master or Slave) Data Received Interrupt Wakeup from Idle Mode In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode Two-wire Start Condition Detector with Interrupt Capability
14.2
Overview
The Universal Serial Interface (USI), provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are included to minimize the processor load. A simplified block diagram of the USI is shown in Figure 14-1 on page 100. For actual placement of I/O pins, refer to "Pinout of ATTINY43U" on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the "Register Descriptions" on page 107. Figure 14-1. Universal Serial Interface, Block Diagram
DQ LE
Bit7 Bit0 DO (Output only)
DI/SDA 3 2 1 0 TIM0 COMP
(Input/Open Drain)
USIDR
USIDB
3 2 1 0 [1] 0 1
CLOCK HOLD
DATA BUS
USIOIF
USISIF
USIDC
USIPF
4-bit Counter
USCK/SCL
(Input/Open Drain)
USISR
2
Two-wire Clock Control Unit
USIWM1
USIWM0
USICS1
USICS0
USICLK
USIOIE
USISIE
USICR
The 8-bit USI Data Register (USIDR) contains the incoming and outgoing data. It is directly accessible via the data bus but a copy of the contents is also placed in the USI Buffer Register (USIBR) where it can be retrieved later. If reading the USI Data Register directly, the register must be read as quickly as possible to ensure that no data is lost. The most significant bit of the USI Data Register is connected to one of two output pins (depending on the mode configuration, see Table 14-1 on page 108). There is a transparent latch between the output of the USI Data Register and the output pin, which delays the change of data 100
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USITC
output to the opposite clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin independent of the configuration. The 4-bit counter can be both read and written via the data bus, and it can generate an overflow interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same clock source. This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. This means the counter registers the number of clock edges and not the number of data bits. The clock can be selected from three different sources: The USCK pin, Timer/Counter0 Compare Match or from software. The two-wire clock control unit can be configured to generate an interrupt when a start condition has been detected on the two-wire bus. It can also be set to generate wait states by holding the clock pin low after a start condition is detected, or after the counter overflows.
14.3
14.3.1
Functional Descriptions
Three-wire Mode The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names used by this mode are: DI, DO, and USCK. Figure 14-2. Three-wire Mode Operation, Simplified Diagram
DO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DI
USCK SLAVE
DO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DI
USCK
PORTxn MASTER
Figure 14-2 shows two USI units operating in three-wire mode, one as Master and one as Slave. The two USI Data Registers are interconnected in such way that after eight USCK clocks, the data in each register has been interchanged. The same clock also increments the USI's 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORTA register or by writing a one to bit USITC bit in USICR.
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Figure 14-3. Three-wire Mode, Timing Diagram
CYCLE USCK USCK DO DI
MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
( Reference ) 1 2 3 4 5 6 7 8
A
B
C
D
E
The three-wire mode timing is shown in Figure 14-3 At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for both external clock modes. In external clock mode 0 (USICS0 = 0), DI is sampled at positive edges, and DO is changed (USI Data Register is shifted by one) at negative edges. In external clock mode 1 (USICS0 = 1) the opposite edges with respect to mode 0 are used. In other words, data is sampled at negative and output is changed at positive edges. The USI clock modes corresponds to the SPI data mode 0 and 1. Referring to the timing diagram (Figure 14-3), a bus transfer involves the following steps: 1. The slave and master devices set up their data outputs and, depending on the protocol used, enable their output drivers (mark A and B). The output is set up by writing the data to be transmitted to the USI Data Register. The output is enabled by setting the corresponding bit in the Data Direction Register of Port A. Note that there is not a preferred order of points A and B in the figure, but both must be at least one half USCK cycle before point C, where the data is sampled. This is in order to ensure that the data setup requirement is satisfied. The 4-bit counter is reset to zero. 2. The master software generates a clock pulse by toggling the USCK line twice (C and D). The bit values on the data input (DI) pins are sampled by the USI on the first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter will count both edges. 3. Step 2. is repeated eight times for a complete register (byte) transfer. 4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that the transfer has been completed. If USI Buffer Registers are not used the data bytes that have been transferred must now be processed before a new transfer can be initiated. The overflow interrupt will wake up the processor if it is set to Idle mode. Depending on the protocol used the slave device can now set its output to high impedance. 14.3.2 SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master:
SPITransfer: out ldi out ldi USIDR,r16 r16,(1<
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SPITransfer_loop: out in sbrs rjmp in ret USICR,r17 r16, USISR r16, USIOIF SPITransfer_loop r16,USIDR
The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function is called is transferred to the slave device, and when the transfer is completed the data received from the slave is stored back into the register r16. The second and third instructions clear the USI Counter Overflow Flag and the USI counter value. The fourth and fifth instructions set three-wire mode, positive edge clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI as an SPI master with maximum speed (fSCK = fCK/2):
SPITransfer_Fast: out ldi ldi out out out out out out out out out out out out out out out out in ret USIDR,r16 r16,(1<103
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14.3.3
SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave:
init: ldi out ... SlaveSPITransfer: out ldi out in sbrs rjmp in ret USIDR,r16 r16,(1<SlaveSPITransfer_loop:
The code is size optimized using only eight instructions (plus return). The code example assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored in register r16 prior to the function is called is transferred to the master device, and when the transfer is completed the data received from the master is stored back into the register r16. Note that the first two instructions are for initialization, only, and need only be executed once. These instructions set three-wire mode and positive edge clock. The loop is repeated until the USI Counter Overflow Flag is set. 14.3.4 Two-wire Mode The USI two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate limiting on outputs and without input noise filtering. Pin names used in this mode are SCL and SDA. Figure 14-4 shows two USI units operating in two-wire mode, one as master and one as slave. It is only the physical layer that is shown since the system operation is highly dependent of the communication scheme used. The main differences between the master and slave operation at this level is the serial clock generation which is always done by the master. Only the slave uses the clock control unit. Clock generation must be implemented in software, but the shift operation is done automatically in both devices. Note that clocking only on negative edges for shifting data is of practical use in this mode. The slave can insert wait states at start or end of transfer by forcing the SCL clock low. This means that the master must always check if the SCL line was actually released after it has generated a positive edge. Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. The clock is generated by the master by toggling the USCK pin via the PORTA register.
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Figure 14-4. Two-wire Mode Operation, Simplified Diagram
VCC
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SDA
SCL
HOLD SCL
Two-wire Clock Control Unit SLAVE
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SDA
SCL PORTxn MASTER
The data direction is not given by the physical layer. A protocol, like the one used by the TWIbus, must be implemented to control the data flow. Figure 14-5. Two-wire Mode, Typical Timing Diagram
SDA SCL
S 1-7 8 9 1-8 9 1-8 9 P
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
A
B
C
D
E
F
Referring to the timing diagram (Figure 14-5), a bus transfer involves the following steps: 1. The start condition is generated by the master by forcing the SDA low line while keeping the SCL line high (A). SDA can be forced low either by writing a zero to bit 7 of the USI Data Register, or by setting the corresponding bit in the PORTA register to zero. Note that the Data Direction Register bit must be set to one for the output to be enabled. The start detector logic of the slave device (see Figure 14-6 on page 106)
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detects the start condition and sets the USISIF Flag. The flag can generate an interrupt if necessary. 2. In addition, the start detector will hold the SCL line low after the master has forced a negative edge on this line (B). This allows the slave to wake up from sleep or complete other tasks before setting up the USI Data Register to receive the address. This is done by clearing the start condition flag and resetting the counter. 3. The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data and shifts it into the USI Data Register at the positive edge of the SCL clock. 4. After eight bits containing slave address and data direction (read or write) have been transferred, the slave counter overflows and the SCL line is forced low (D). If the slave is not the one the master has addressed, it releases the SCL line and waits for a new start condition. 5. When the slave is addressed, it holds the SDA line low during the acknowledgment cycle before holding the SCL line low again (i.e., the USI Counter Register must be set to 14 before releasing SCL at (D)). Depending on the R/W bit the master or slave enables its output. If the bit is set, a master read operation is in progress (i.e., the slave drives the SDA line) The slave can hold the SCL line low after the acknowledge (E). 6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is given by the master (F), or a new start condition is given. If the slave is not able to receive more data it does not acknowledge the data byte it has last received. When the master does a read operation it must terminate the operation by forcing the acknowledge bit low after the last byte transmitted. 14.3.5 Start Condition Detector The start condition detector is shown in Figure 14-6. The SDA line is delayed (in the range of 50 to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled in two-wire mode. Figure 14-6. Start Condition Detector, Logic Diagram
USISIF CLOCK HOLD
DQ SDA
CLR
DQ
CLR
SCL Write( USISIF)
The start condition detector works asynchronously and can therefore wake up the processor from power-down sleep mode. However, the protocol used might have restrictions on the SCL hold time. Therefore, when using this feature the oscillator start-up time (set by CKSEL fuses, see "Clock Sources" on page 24) must also be taken into consideration. Refer to the description of the USISIF bit on page 112 for further details.
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14.4
Alternative USI Usage
The flexible design of the USI allows it to be used for other tasks when serial communication is not needed. Below are some examples.
14.4.1
Half-Duplex Asynchronous Data Transfer Using the USI Data Register in three-wire mode it is possible to implement a more compact and higher performance UART than by software, only. 4-Bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the counter is clocked externally, both clock edges will increment the counter value.
14.4.2
14.4.3
12-Bit Timer/Counter Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter. Edge Triggered External Interrupt By setting the counter to maximum value (F) it can function as an additional external interrupt. The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature is selected by the USICS1 bit. Software Interrupt The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
14.4.4
14.4.5
14.5
14.5.1
Register Descriptions
USICR - USI Control Register
Bit 0x0D (0x2D) Read/Write Initial Value 7 USISIE R/W 0 6 USIOIE R/W 0 5 USIWM1 R/W 0 4 USIWM0 R/W 0 3 USICS1 R/W 0 2 USICS0 R/W 0 1 USICLK W 0 0 USITC W 0 USICR
The Control Register includes interrupt enable control, wire mode setting, Clock Select setting, and clock strobe. * Bit 7 - USISIE: Start Condition Interrupt Enable Setting this bit to one enables the Start Condition detector interrupt. If there is a pending interrupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed. See the USISIF bit description in "Analog Comparator" on page 112 for further details. * Bit 6 - USIOIE: Counter Overflow Interrupt Enable Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt when the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed. See the USIOIF bit description in "Analog Comparator" on page 112 for further details. * Bit 5:4 - USIWM[1:0]: Wire Mode These bits set the type of wire mode to be used. Basically only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and Shift Register can therefore be clocked exter-
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nally, and data input sampled, even when outputs are disabled. The relations between USIWM1..0 and the USI operation is summarized in Table 14-1. Table 14-1.
USIWM1 0
Relationship between USIWM[1:0] and USI Operation
USIWM0 0 Description Outputs, clock hold, and start detector disabled. Port pins operate as normal. Three-wire mode. Uses DO, DI, and USCK pins. The Data Output (DO) pin overrides the corresponding bit in the PORTA register. However, the corresponding DDRA bit still controls the data direction. When the port pin is set as input the pin pull-up is controlled by the PORTA bit. The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port operation. When operating as master, clock pulses are software generated by toggling the PORTA register, while the data direction is set to output. The USITC bit in the USICR Register can be used for this purpose. Two-wire mode. Uses SDA (DI) and SCL (USCK) pins(1). The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and use open-collector output drives. The output drivers are enabled by setting the corresponding bit for SDA and SCL in the DDRA register. When the output driver is enabled for the SDA pin, the output driver will force the line SDA low if the output of the USI Data Register or the corresponding bit in the PORTA register is zero. Otherwise, the SDA line will not be driven (i.e., it is released). When the SCL pin output driver is enabled the SCL line will be forced low if the corresponding bit in the PORTA register is zero, or by the start detector. Otherwise the SCL line will not be driven. The SCL line is held low when a start detector detects a start condition and the output is enabled. Clearing the Start Condition Flag (USISIF) releases the line. The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on the SDA and SCL port pin are disabled in Two-wire mode. Two-wire mode. Uses SDA and SCL pins. Same operation as in two-wire mode above, except that the SCL line is also held low when a counter overflow occurs, and until the Counter Overflow Flag (USIOIF) is cleared.
0
1
1
0
1
1
Note:
1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively to avoid confusion between the modes of operation.
* Bit 3:2 - USICS[1:0]: Clock Source Select These bits set the clock source for the USI Data Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the data input (DI/SDA) when using external clock source (USCK/SCL). When software strobe or Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and therefore the output is changed immediately. Clearing the USICS[1:0] bits enables software strobe option. When using this option, writing a one to the USICLK bit clocks both the USI Data Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external clocking and software clocking by the USITC strobe bit.
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Table 14-2 shows the relationship between the USICS[1:0] and USICLK setting and clock source used for the USI Data Register and the 4-bit counter. Table 14-2.
USICS1 0 0 0 1 1 1 1
Relationship between the USICS1:0 and USICLK Setting
USICS0 0 0 1 0 1 0 1 USICLK 0 1 X 0 0 1 1 Clock Source No Clock Software clock strobe (USICLK) Timer/Counter0 Compare Match External, positive edge External, negative edge External, positive edge External, negative edge 4-bit Counter Clock Source No Clock Software clock strobe (USICLK) Timer/Counter0 Compare Match External, both edges External, both edges Software clock strobe (USITC) Software clock strobe (USITC)
* Bit 1 - USICLK: Clock Strobe Writing a one to this bit location strobes the USI Data Register to shift one step and the counter to increment by one, provided that the software clock strobe option has been selected by writing USICS1:0 bits to zero. The output will change immediately when the clock strobe is executed, i.e., during the same instruction cycle. The value shifted into the USI Data Register is sampled the previous instruction cycle. When an external clock source is selected (USICS1 = 1), the USICLK function is changed from a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the USITC strobe bit as clock source for the 4-bit counter (see Table 14-2). The bit will be read as zero. * Bit 0 - USITC: Toggle Clock Port Pin Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0. The toggling is independent of the setting in the Data Direction Register, but if the PORT value is to be shown on the pin the corresponding DDR pin must be set as output (to one). This feature allows easy clock generation when implementing master devices. When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of when the transfer is done when operating as a master device. The bit will read as zero. 14.5.2 USISR - USI Status Register
Bit 0x0E (0x2E) Read/Write Initial Value 7
USISIF
6
USIOIF
5
USIPF
4
USIDC
3
USICNT3
2
USICNT2
1
USICNT1
0
USICNT0 USISR
R/W 0
R/W 0
R/W 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
The Status Register contains interrupt flags, line status flags and the counter value. * Bit 7 - USISIF: Start Condition Interrupt Flag When two-wire mode is selected, the USISIF Flag is set (to one) when a start condition has been detected. When three-wire mode or output disable mode has been selected any edge on the SCK pin will set the flag.
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If USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be generated when this flag is set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing this bit will release the start detection hold of USCL in two-wire mode. A start condition interrupt will wakeup the processor from all sleep modes. * Bit 6 - USIOIF: Counter Overflow Interrupt Flag This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). If the USIOIE bit in USICR and the Global Interrupt Enable Flag are set an interrupt will also be generated when the flag is set. The flag will only be cleared if a one is written to the USIOIF bit. Clearing this bit will release the counter overflow hold of SCL in two-wire mode. A counter overflow interrupt will wakeup the processor from Idle sleep mode. * Bit 5 - USIPF: Stop Condition Flag When two-wire mode is selected, the USIPF Flag is set (one) when a stop condition has been detected. The flag is cleared by writing a one to this bit. Note that this is not an interrupt flag. This signal is useful when implementing two-wire bus master arbitration. * Bit 4 - USIDC: Data Output Collision This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The flag is only valid when two-wire mode is used. This signal is useful when implementing Two-wire bus master arbitration. * Bits 3:0 - USICNT[3:0]: Counter Value These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or written by the CPU. The 4-bit counter increments by one for each clock generated either by the external clock edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe bits. The clock source depends on the setting of the USICS1:0 bits. For external clock operation a special feature is added that allows the clock to be generated by writing to the USITC strobe bit. This feature is enabled by choosing an external clock source (USICS1 = 1) and writing a one to the USICLK bit. Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input (USCK/SCL) can still be used by the counter. 14.5.3 USIDR - USI Data Register
Bit 0x0F (0x2F) Read/Write Initial Value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 USIDR
The USI Data Register can be accessed directly but a copy of the data can also be found in the USI Buffer Register. Depending on the USICS[1:0] bits of the USI Control Register a (left) shift operation may be performed. The shift operation can be synchronised to an external clock edge, to a Timer/Counter0 Compare Match, or directly to software via the USICLK bit. If a serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed.
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Note that even when no wire mode is selected (USIWM[1:0] = 0) both the external data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register. The output pin (DO or SDA, depending on the wire mode) is connected via the output latch to the most significant bit (bit 7) of the USI Data Register. The output latch ensures that data input is sampled and data output is changed on opposite clock edges. The latch is open (transparent) during the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1) and constantly open when an internal clock source is used (USICS1 = 0). The output will be changed immediately when a new MSB is written as long as the latch is open. Note that the Data Direction Register bit corresponding to the output pin must be set to one in order to enable data output from the USI Data Register. 14.5.4 USIBR - USI Data Buffer
Bit 0x10 (0x30) Read/Write Initial Value 7 MSB R 0 R 0 R 0 R 0 R 0 R 0 R 0 6 5 4 3 2 1 0 LSB R 0 USIBR
Instead of reading data from the USI Data Register the USI Buffer Register can be used. This makes controlling the USI less time critical and gives the CPU more time to handle other program tasks. USI flags as set similarly as when reading the USIDR register. The content of the USI Data Register is loaded to the USI Buffer Register when the transfer has been completed.
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15. Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 15-1 on page 112. Figure 15-1. Analog Comparator Block Diagram
BANDGAP REFERENCE ACBG
ACME ADEN ADC MULTIPLEXER OUTPUT (1)
Notes:
1. See Table 15-1 on page 113.
See Figure 1-1 on page 2 and Table 11-3 on page 70 for Analog Comparator pin placement. The ADC Power Reduction bit, PRADC, must be disabled in order to use the ADC input multiplexer. This is done by clearing the PRADC bit in the Power Reduction Register, PRR. See "PRR - Power Reduction Register" on page 35 for more details.
15.1
Analog Comparator Multiplexed Input
It is possible to select any of the ADC[3:0] pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX[1:0] in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 15-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator.
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Table 15-1.
ACME 0 1 1 1 1 1
Analog Comparator Multiplexed Input
ADEN X 1 0 0 0 0 MUX2..0 XXX XXX 000 001 010 011 Analog Comparator Negative Input AIN1 AIN1 ADC0 ADC1 ADC2 ADC3
15.2
15.2.1
Register Description
ADCSRB - ADC Control and Status Register B
Bit 0x03 (0x23) Read/Write Initial Value 7 BS R 0 6 ACME R/W 0 5 - R/W 0 4 ADLAR R/W 0 3 - R/W 0 2 ADTS2 R/W 0 1 ADTS1 R/W 0 0 ADTS0 R/W 0 ADCSRB
* Bit 6 - ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see "Analog Comparator Multiplexed Input" on page 112. 15.2.2 ACSR - Analog Comparator Control and Status Register
Bit 0x08 (0x28) Read/Write Initial Value 7 ACD R/W 0 6 ACBG R/W 0 5 ACO R/W N/A 4 ACI R/W 0 3 ACIE R/W 0 2 - R 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR
* Bit 7 - ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. * Bit 6 - ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. * Bit 5 - ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles.
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* Bit 4 - ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. * Bit 3 - ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled. * Bit 2 - Res: Reserved Bit These bits are reserved and will always read zero. * Bits 1, 0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 15-2. Table 15-2.
ACIS1 0 0 1 1
ACIS1/ACIS0 Settings
ACIS0 0 1 0 1 Interrupt Mode Comparator Interrupt on Output Toggle. Reserved Comparator Interrupt on Falling Output Edge. Comparator Interrupt on Rising Output Edge.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. 15.2.3 DIDR0 - Digital Input Disable Register 0
Bit 0x01 (0x21) Read/Write Initial Value 7 - R 0 6 - R 0 5 AIN1D R/W 0 4 AIN0D R/W 0 3 ADC3D R/W 0 2 ADC2D R/W 0 1 ADC1D R/W 0 0 ADC0D R/W 0 DIDR0
* Bits 7, 6 - Res: Reserved Bits These bits are reserved and will always read zero. * Bits 5, 4 - AIN1D, AIN0D: Analog Comparator I/O When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
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16. Analog to Digital Converter
16.1 Features
* * * * * * * * * * * * * *
10-bit Resolution 1 LSB Integral Non-linearity 2 LSB Absolute Accuracy 13s Conversion Time 15 kSPS at Maximum Resolution Four Multiplexed Single Ended Input Channels Temperature Sensor Input Channel Optional Left Adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range 1.1V ADC Reference Voltage Free Running or Single Conversion Mode ADC Start Conversion by Auto Triggering on Interrupt Sources Interrupt on ADC Conversion Complete Sleep Mode Noise Cancele
16.2
Overview
ATTINY43U features a 10-bit, successive approximation Analog-to-Digital Converter (ADC). A block diagram of the ADC is shown in Figure 16-1. Figure 16-1. Analog to Digital Converter Block Schematic
8-BIT DATA BUS
ADMUX
MUX2:0 ADLAR REFS
ADCSRB
ADTS2:0
INTERRUPT FLAGS
ADCSRA
ADPS2 ADPS1 ADPS0 ADSC ADATE ADEN ADIE
ADCH+ADCL
DECODER
CHANNEL
TRIGGER SELECT
START
ADC IRQ
PRESCALER
ADC9:0 ADIF
CONVERSION LOGIC VCC INTERNAL REFERENCE TEMPERATURE SENSOR 10-BIT DAC +
SAMPLE & HOLD COMPARATOR
VBAT ADC3 ADC2 ADC1 ADC0
1/2 INPUT MUX
ADC MUX OUTPUT
AGND
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The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. The analog multiplexer allows eight single-ended channels to be connected to the ADC, including the low four bits of port A, the internal temperature sensor, the internal voltage reference, supply voltage (VBAT) and ground (GND). Internal reference voltage of nominally 1.1V is provided on-chip. Alternatively, VCC can be used as reference voltage.
16.3
ADC Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the reference voltage.The voltage reference for the ADC may be selected by writing to the REFS bit in ADMUX. The VCC supply or an internal 1.1V voltage reference may be selected as the ADC voltage reference. The analog input channel is selected by writing to the MUX2..0 bits in ADMUX. Any of the four ADC input pins ADC3..0, and VBAT input pin can be selected as single ended input to the ADC. The on-chip temperature sensor is selected by writing "111" to the MUX2..0 bits in the ADMUX register. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADCSRB. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost.
16.4
Starting a Conversion
Make sure the ADC is powered by clearing the ADC Power Reduction bit, PRADC, in the Power Reduction Register, PRR (see "PRR - Power Reduction Register" on page 35). A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS
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bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next interrupt event. Figure 16-2. ADC Auto Trigger Logic
ADTS[2:0] PRESCALER
START ADIF SOURCE 1 . . . . SOURCE n ADSC ADATE
CLKADC
CONVERSION LOGIC EDGE DETECTOR
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started.
16.5
Prescaling and Conversion Timing
By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. It is not recommended to use a higher input clock frequency than 1 MHz. The ADC module contains a prescaler, as illustrated in Figure 16-3 on page 118, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low.
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Figure 16-3. ADC Prescaler
ADEN START CK Reset 7-BIT ADC PRESCALER
ADPS0 ADPS1 ADPS2
ADC CLOCK SOURCE
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles, as summarised in Table 16-1 on page 120. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry, as shown in Figure 16-4 below. Figure 16-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
First Conversion Next Conversion
Cycle Number
1
2
12
13
14
15
16
17
CK/128
24
CK/16
CK/32
CK/64
CK/2
CK/4
CK/8
18
19
20
21
22
23
25
1
2
3
ADC Clock ADEN ADSC ADIF ADCH ADCL Sign and MSB of Result LSB of Result
MUX and REFS Update
Sample & Hold
Conversion Complete
MUX and REFS Update
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of a first conversion. See Figure 16-5. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.
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Figure 16-5. ADC Timing Diagram, Single Conversion
One Conversion Next Conversion
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete
MUX and REFS Update
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in Figure 16-6 below. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock cycles are used for synchronization logic. Figure 16-6. ADC Timing Diagram, Auto Triggered Conversion
One Conversion Next Conversion
Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete Prescaler Reset
Prescaler Reset
In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. See Figure 16-7.
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Figure 16-7. ADC Timing Diagram, Free Running Conversion
One Conversion 11 12 13 Next Conversion 1 2 3 4
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
Sign and MSB of Result LSB of Result
Conversion Complete
Sample & Hold MUX and REFS Update
For a summary of conversion times, see Table 16-1. Table 16-1.
Condition First conversion Normal conversions Auto Triggered conversions Free Running conversion
ADC Conversion Time
Sample & Hold (Cycles from Start of Conversion) 13.5 1.5 2 2.5 Conversion Time (Cycles) 25 13 13.5 14
16.6
Changing Channel or Reference Selection
The MUX[2:0] and REFS bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings.
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If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: * When ADATE or ADEN is cleared. * During conversion, minimum one ADC clock cycle after the trigger event. * After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. 16.6.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: * In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. * In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 16.6.2 ADC Voltage Reference The ADC reference voltage (VREF) indicates the conversion range for the ADC. Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either VCC, or internal 1.1V reference, or external AREF pin. The internal 1.1V reference is generated from the internal bandgap reference (VBG) through an internal amplifier. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result.
16.7
ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode. This reduces noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: * Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. * Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. * If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC
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conversion completes. The CPU will remain in active mode until a new sleep command is executed.
Note that the ADC will not automatically be turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption.
16.8
Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 16-8. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10k or less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, which can vary widely. With slowly varying signals the user is recommended to use sources with low impedance, only, since this minimizes the required charge transfer to the S/H capacitor. In order to avoid distortion from unpredictable signal convolution, signal components higher than the Nyquist frequency (fADC/2) should not be present. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 16-8. Analog Input Circuitry
IIH ADCn 1..100 kohm CS/H= 14 pF IIL VCC/2
Note: The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and any stray or parasitic capacitance inside the device. The value given is worst case.
16.9
Analog Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: * Keep analog signal paths as short as possible. * Make sure analog tracks run over the analog ground plane.
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* Keep analog tracks well away from high-speed switching digital tracks. * Use the ADC noise canceler function to reduce induced noise from the CPU. * If any port pin is used as a digital output, it mustn't switch while a conversion is in progress. * Place bypass capacitors as close to VCC and GND pins as possible. Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as described in Section 16.7 on page 121. This is especially the case when system clock frequency is above 1 MHz, or when the ADC is used for reading the internal temperature sensor. A good system design with properly placed, external bypass capacitors does reduce the need for using ADC Noise Reduction Mode
16.10 ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior:
* Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. Figure 16-9. Offset Error
Output Code
Ideal ADC Actual ADC
Offset Error
VREF Input Voltage
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* Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 16-10. Gain Error
Output Code
Gain Error
Ideal ADC Actual ADC
VREF Input Voltage
* Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. Figure 16-11. Integral Non-linearity (INL)
Output Code
INL
Ideal ADC Actual ADC VREF Input Voltage
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* Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 16-12. Differential Non-linearity (DNL)
Output Code 0x3FF
1 LSB
DNL
0x000 0 VREF Input Voltage
* Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always 0.5 LSB. * Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: 0.5 LSB
16.11 ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). For single ended conversion, the result is V IN 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 16-3 on page 126 and Table 16-4 on page 127). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB. The result is presented in onesided form, from 0x3FF to 0x000.
16.12 Temperature Measurement
The temperature measurement is based on an on-chip temperature sensor that is coupled to a single ended ADC channel. Selecting the ADC4 channel by writing the MUX2:0 bits in ADMUX register to "111" enables the temperature sensor. The internal 1.1V reference must also be selected for the ADC reference source in the temperature sensor measurement. When the tem-
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perature sensor is enabled, the ADC converter can be used in single conversion mode to measure the voltage over the temperature sensor. The measured voltage has a linear relationship to the temperature as described in Table 16-2 The sensitivity is approximately 1 LSB / C and the accuracy depends on the method of user calibration. Typically, the measurement accuracy after a single temperature calibration is 10C, assuming calibration at room temperature. Better accuracies are achieved by using two temperature points for calibration. Table 16-2.
Temperature ADC
Temperature vs. Sensor Output Voltage (Typical Case)
-40 C 230 LSB +25 C 300 LSB +85 C 370 LSB
The values described in Table 16-2 are typical values. However, due to process variation the temperature sensor output voltage varies from one chip to another. To be capable of achieving more accurate results the temperature measurement can be calibrated in the application software. The sofware calibration can be done using the formula:
T = k * [(ADCH << 8) | ADCL] + TOS
where ADCH and ADCL are the ADC data registers, k is the fixed slope coefficient and TOS is the temperature sensor offset. Typically, k is very close to 1.0 and in single-point calibration the coefficient may be omitted. Where higher accuracy is required the slope coefficient should be evaluated based on measurements at two temperatures.
16.13 Register Description
16.13.1 ADMUX - ADC Multiplexer Selection Register
Bit 0x07 (0x27) Read/Write Initial Value 7
-
6 REFS R/W 0
5
-
4
-
3
-
2 MUX2 R/W 0
1 MUX1 R/W 0
0 MUX0 R/W 0 ADMUX
R/W 0
R 0
R 0
R 0
* Bit 7 - Res: Reserved Bit This bit is reserved and must always be written zero. * Bit 6 - REFS: Reference Selection Bit This bit selects the voltage reference for the ADC, as shown in Table 16-3 on page 126. If this bit is changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSR is set). Table 16-3. Voltage Reference Selections for ADC
Voltage Reference Selection VCC used as analog reference. Internal 1.1V Voltage Reference.
REFS 0 1
* Bits 5:3 - Res: Reserved Bits These bits are reserved and will always read zero.
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* Bits 2:0 - MUX[2:0]: Analog Channel Selection Bits The value of these bits selects which analog input is connected to the ADC, as shown in Table 16-4. Selecting channel ADC4 enables temperature measurement. Table 16-4. ADC Multiplexer Channel Selections.
Single Ended Input ADC0 (PA0) ADC1 (PA1) ADC2 (PA2) ADC3 (PA3) 0V (GND) 1.1V (I Ref) MUX[2:0] 000 001 010 011 100 101 110 111
VBAT (1)
ADC4 Notes:
(2)
1. Due to the voltage divider present, a current will flow from VBAT to ground via a 100k resistor divider as long as this channel is selected. 2. See "Temperature Measurement" on page 125.
If these bits are changed during a conversion, the change will not go into effect until this conversion is complete (ADIF in ADCSRA is set). 16.13.2 ADCSRA - ADC Control and Status Register A
Bit 0x06 (0x26) Read/Write Initial Value 7 ADEN R/W 0 6 ADSC R/W 0 5 ADATE R/W 0 4 ADIF R/W 0 3 ADIE R/W 0 2 ADPS2 R/W 0 1 ADPS1 R/W 0 0 ADPS0 R/W 0 ADCSRA
* Bit 7 - ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. * Bit 6 - ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. * Bit 5 - ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.
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* Bit 4 - ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the data registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI instruction is used. * Bit 3 - ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated. * Bits 2:0 - ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the system clock frequency and the input clock to the ADC. Table 16-5.
ADPS2 0 0 0 0 1 1 1 1
ADC Prescaler Selections
ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 Division Factor 2 2 4 8 16 32 64 128
16.13.3 16.13.3.1
ADCL and ADCH - ADC Data Register ADLAR = 0
Bit 0x05 (0x25) 0x04 (0x24) 15 - ADC7 7 Read/Write R R Initial Value 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL
16.13.3.2
ADLAR = 1
Bit 0x05 (0x25) 0x04 (0x24) 15 ADC9 ADC1 7 Read/Write R R Initial Value 0 0 14 ADC8 ADC0 6 R R 0 0 13 ADC7 - 5 R R 0 0 12 ADC6 - 4 R R 0 0 11 ADC5 - 3 R R 0 0 10 ADC4 - 2 R R 0 0 9 ADC3 - 1 R R 0 0 8 ADC2 - 0 R R 0 0 ADCH ADCL
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When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADCSRB, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. * ADC[9:0]: ADC Conversion Result These bits represent the result from the conversion, as detailed in "ADC Conversion Result" on page 125. 16.13.4 ADCSRB - ADC Control and Status Register B
Bit 0x03 (0x23) Read/Write Initial Value 7 BS R 0 6 ACME R/W 0 5 - R/W 0 4 ADLAR R/W 0 3 - R/W 0 2 ADTS2 R/W 0 1 ADTS1 R/W 0 0 ADTS0 R/W 0 ADCSRB
* Bit 5 - Res: Reserved Bit This bit is reserved and will always read what was written. * Bit 4 - ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a comple the description of this bit, see "ADCL and ADCH - ADC Data Register" on page 128. * Bit 3 - Res: Reserved Bit This bit is reserved and will always read what was written. * Bits 2:0 - ADTS[2:0]: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. Table 16-6.
ADTS2 0 0 0 0 1
ADC Auto Trigger Source Selections
ADTS1 0 0 1 1 0 ADTS0 0 1 0 1 0 Trigger Source Free Running mode Analog Comparator External Interrupt Request 0 Timer/Counter0 Compare Match A Timer/Counter0 Overflow
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Table 16-6.
ADTS2 1 1 1
ADC Auto Trigger Source Selections (Continued)
ADTS1 0 1 1 ADTS0 1 0 1 Trigger Source Timer/Counter1 Compare Match A Timer/Counter1 Overflow Timer/Counter1 Compare Match B
16.13.5
DIDR0 - Digital Input Disable Register 0
Bit 0x01 (0x21) Read/Write Initial Value 7 - R 0 6 - R 0 5 AIN1D R/W 0 4 AIN0D R/W 0 3 ADC3D R/W 0 2 ADC2D R/W 0 1 ADC1D R/W 0 0 ADC0D R/W 0 DIDR0
* Bits 3:0 - ADC[3:0]D: ADC[3:0] Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC[3:0] pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
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17. debugWIRE On-chip Debug System
17.1 Features
* * * * * * * * * *
Complete Program Flow Control Emulates All On-chip Functions, Both Digital and Analog , except RESET Pin Real-time Operation Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs) Unlimited Number of Program Break Points (Using Software Break Points) Non-intrusive Operation Electrical Characteristics Identical to Real Device Automatic Configuration System High-Speed Operation Programming of Non-volatile Memories
17.2
Overview
The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the program flow, execute AVR instructions in the CPU and to program the different non-volatile memories.
17.3
Physical Interface
When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. Figure 17-1. The debugWIRE Setup
1.8 - 5.5V
VCC
dW
dW(RESET)
GND
Figure 17-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses.
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When designing a system where debugWIRE will be used, the following observations must be made for correct operation: * Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 k. However, the pull-up resistor is optional. * Connecting the RESET pin directly to VCC will not work. * Capacitors inserted on the RESET pin must be disconnected when using debugWire. * All external reset sources must be disconnected.
17.4
Software Break Points
debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a Break Point in AVR Studio(R) will insert a BREAK instruction in the Program memory. The instruction replaced by the BREAK instruction will be stored. When program execution is continued, the stored instruction will be executed before continuing from the Program memory. A break can be inserted manually by putting the BREAK instruction in the program. The Flash must be re-programmed each time a Break Point is changed. This is automatically handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore reduce the Falsh Data retention. Devices used for debugging purposes should not be shipped to end customers.
17.5
Limitations of debugWIRE
The debugWIRE communication pin (dW) is physically located on the same pin as External Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is enabled. The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e., when the program in the CPU is running. When the CPU is stopped, care must be taken while accessing some of the I/O Registers via the debugger (AVR Studio). See the debugWIRE documentation for detailed description of the limitations. A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should be disabled when debugWire is not used.
17.6
Register Description
The following section describes the registers used with the debugWire.
17.6.1
DWDR - debugWire Data Register
Bit 0x27 (0x47) Read/Write Initial Value R/W 0 R/W 0 R/W 0 7 6 5 4 3 2 1 0 DWDR R/W 0 R/W 0 R/W 0 DWDR[7:0] R/W 0 R/W 0
The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations.
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18. Self-Programming the Flash
The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The SPM instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse (to "0"). The Program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write operation: Alternative 1, fill the buffer before a Page Erase * Fill temporary page buffer * Perform a Page Erase * Perform a Page Write
Alternative 2, fill the buffer after Page Erase * Perform a Page Erase * Fill temporary page buffer * Perform a Page Write If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be re-written. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page.
18.1
Performing Page Erase by SPM
To execute Page Erase, set up the address in the Z-pointer, write "00000011" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. * The CPU is halted during the Page Erase operation.
18.2
Filling the Temporary Buffer (Page Loading)
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write "00000001" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address the data in the temporary buffer. The temporary buffer will auto-erase after a Page Write operation or by writing the CTPB bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost.
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18.3
Performing a Page Write
To execute Page Write, set up the address in the Z-pointer, write "00000101" to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. * The CPU is halted during the Page Write operation.
18.4
Addressing the Flash During Self-Programming
The Z-pointer is used to address the SPM commands.
Bit ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0
Since the Flash is organized in pages (see Table 19-8 on page 142), the Program Counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. This is shown in Figure 19-7 on page 151. Note that the Page Erase and Page Write operations are addressed independently. Therefore it is of major importance that the software addresses the same page in both the Page Erase and Page Write operation. The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used. Figure 18-1. Addressing the Flash During SPM(1)
BIT Z - REGISTER PCMSB PROGRAM COUNTER
PCPAGE
15
ZPCMSB
ZPAGEMSB
10 0
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. The different variables used in Figure 18-1 are listed in Table 19-8 on page 142.
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18.5
EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register.
18.6
Reading the Fuse and Lock Bits from Software
It is possible for firmware to read device fuse and lock bits. In addition, firmware can also read data from the device signature imprint table (see page 141).
Note: Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one.
18.6.1
Reading Lock Bits from Firmware Lock bit values are returned in the destination register after an LPM instruction has been issued within three CPU cycles after RFLB and SPMEN bits have been set in SPMCSR. The RFLB and SPMEN bits automatically clear upon completion of reading the lock bits, or if no LPM instruction is executed within three CPU cycles, or if no SPM instruction is executed within four CPU cycles. When RFLB and SPMEN are cleared LPM functions normally. To read the lock bits, follow the below procedure: 1. Load the Z-pointer with 0x0001. 2. Set RFLB and SPMEN bits in SPMCSR. 3. Issue an LPM instruction within three clock cycles. 4. Read the lock bits from the LPM destination register. If successful, the contents of the destination register are as follows.
Bit Rd 7 - 6 - 5 - 4 - 3 - 2 - 1 LB2 0 LB1
See section "Program And Data Memory Lock Bits" on page 139 for more information. 18.6.2 Reading Fuse Bits from Firmware The algorithm for reading fuse bytes is similar to the one described above for reading lock bits, only the addresses are different. To read the Fuse Low Byte (FLB), follow the below procedure: 1. Load the Z-pointer with 0x0000. 2. Set RFLB and SPMEN bits in SPMCSR. 3. Issue an LPM instruction within three clock cycles. 4. Read the FLB from the LPM destination register. If successful, the contents of the destination register are as follows.
Bit Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0
Refer to Table 19-5 on page 141 for a detailed description and mapping of the Fuse Low Byte.
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To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows.
Bit Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0
Refer to Table 19-4 on page 140 for detailed description and mapping of the Fuse High Byte. To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and repeat the previous procedure. If successful, the contents of the destination register are as follows.
Bit Rd 7 FEB7 6 FEB6 5 FEB5 4 FEB4 3 FEB3 2 FEB2 1 FEB1 0 FEB0
Refer to Table 19-3 on page 140 for detailed description and mapping of the Fuse Extended Byte. 18.6.3 Reading Device Signature Imprint Table from Firmware To read the contents of the device signature imprint table, follow the below procedure: 1. Load the Z-pointer with the table index. 2. Set RSIG and SPMEN bits in SPMCSR. 3. Issue an LPM instruction within three clock cycles. 4. Read table data from the LPM destination register. See program example below. Assembly Code Example
DSIT_read: ; Uses Z-pointer as table index ldi ldi ldi ZH, 0 ZL, 1 r16, (1<; Preload SPMCSR bits into R16, then write to SPMCSR out SPMCSR, r16 ; Issue LPM. Table data will be returned into r17 lpm r17, Z ret Note: See "Code Examples" on page 6.
If successful, the contents of the destination register are as described in section "Device Signature Imprint Table" on page 141.
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18.7
Preventing Flash Corruption
During periods of low VCC, the Flash program can be corrupted because the supply voltage is too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low VCC reset protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes.
18.8
Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 18-1 shows the typical programming time for Flash accesses from the CPU. Table 18-1. SPM Programming Time
Symbol Flash write (Page Erase, Page Write, and write Lock bits by SPM) Min Programming Time 3.7 ms Max Programming Time 4.5 ms
18.9
18.9.1
Register Description
SPMCSR - Store Program Memory Control and Status Register The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations.
Bit 0x37 (0x57) Read/Write Initial Value 7
-
6
-
5
-
4
CTPB
3
RFLB
2
PGWRT
1
PGERS
0
SPMEN SPMCSR
R 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bits 7:5 - Res: Reserved Bits These bits are reserved and will always read zero. * Bit 4 - CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will be lost.
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* Bit 3 - RFLB: Read Fuse and Lock Bits An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See "EEPROM Write Prevents Writing to SPMCSR" on page 135 for details. * Bit 2 - PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. * Bit 1 - PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation. * Bit 0 - SPMEN: Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than "10001", "01001", "00101", "00011" or "00001" in the lower five bits will have no effect.
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19. Memory Programming
This section describes the different methods for Programming the ATTINY43U memories.
19.1
Program And Data Memory Lock Bits
The ATTINY43U provides two Lock bits which can be left unprogrammed ("1") or can be programmed ("0") to obtain the additional security listed in Table 19-2 on page 139. The Lock bits can only be erased to "1" with the Chip Erase command. The device has no separate boot loader section. The SPM instruction is enabled for the whole Flash, if the SELFPROGEN fuse is programmed ("0"), otherwise it is disabled. Program memory can be read out via the debugWIRE interface when the DWEN fuse is programmed, even if lock bits are set. Thus, when lock bit security is required, debugWIRE should always be disabled by clearing the DWEN fuse. Table 19-1. Lock Bit Byte(1)
Bit No 7 6 5 4 3 2 LB2 LB1 Note: 1 0 Description - - - - - - Lock bit Lock bit Default Value 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed)
Lock Bit Byte
1. "1" means unprogrammed, "0" means programmed
Table 19-2.
Lock Bit Protection Modes.
(2)
Memory Lock Bits (1) LB Mode 1 LB2 1
Protection Type
LB1 1 No memory lock features enabled. Further programming of the Flash and EEPROM is disabled in High-voltage and Serial Programming mode. The Fuse bits are locked in both Serial and High-voltage Programming mode.(1) debugWire is disabled. Further programming and verification of the Flash and EEPROM is disabled in High-voltage and Serial Programming mode. The Fuse bits are locked in both Serial and High-voltage Programming mode.(1) debugWire is disabled.
2
1
0
3
0
0
Notes:
1. Program fuse bits before programming LB1 and LB2. 2. "1" means unprogrammed, "0" means programmed
Lock bits can also be read by device firmware. See section "Reading the Fuse and Lock Bits from Software" on page 135.
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19.2
Fuse Bytes
The ATTINY43U has three Fuse bytes. Table 19-3, Table 19-4 and Table 19-5 briefly describe the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, "0", if they are programmed.. Table 19-3. Fuse Extended Byte
Bit No 7 6 5 4 3 2 1 SELFPRGEN(1) Notes: 0 Description Self-Programming Enable Default Value 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed)
Fuse High Byte
1. Enables SPM instruction. See "Self-Programming the Flash" on page 133.
Table 19-4.
(1)
Fuse High Byte
Bit No 7 6 5 4 3 2 1 0 Description External Reset disable DebugWIRE Enable Enable Serial Program and Data Downloading Watchdog Timer always on EEPROM memory is preserved through the Chip Erase Brown-out Detector trigger level Brown-out Detector trigger level Brown-out Detector trigger level Default Value 1 (unprogrammed) 1 (unprogrammed) 0 (programmed, SPI prog. enabled) 1 (unprogrammed) 1 (unprogrammed, EEPROM not preserved) 1 (unprogrammed) 1 (unprogrammed) 1 (unprogrammed)
Fuse High Byte RSTDISBL DWEN(2) SPIEN(3) WDTON(4) EESAVE BODLEVEL2(5) BODLEVEL1
(5)
BODLEVEL0(5) Notes:
1. See "Alternate Functions of Port B" on page 74 for description of RSTDISBL and DWEN Fuses. When programming the RSTDISBL Fuse, TBD programming has to be used to change fuses to perform further programming 2. DWEN must be unprogrammed when Lock Bit security is required. See "Program And Data Memory Lock Bits" on page 139. 3. The SPIEN Fuse is not accessible in SPI Programming mode. 4. See "WDT Configuration as a Function of the Fuse Settings of WDTON" on page 52 for details. 5. See Table 20-5 on page 158 for BODLEVEL Fuse decoding.
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Table 19-5.
(1)
Fuse Low Byte
Bit No 7 6 5 4 3 2 1 0 Description Divide clock by 8 Clock Output Enable Select start-up time Select start-up time Select Clock source Select Clock source Select Clock source Select Clock source Default Value 0 (programmed) 1 (unprogrammed) 1 (unprogrammed)(2) 0 (programmed)(2) 0 (programmed)(3) 0 (programmed)(3) 1 (unprogrammed)(3) 0 (programmed)(3)
Fuse Low Byte CKDIV8 CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes:
1. See "Power Management and Sleep Modes" on page 31 for details. 2. The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 6-5 on page 26 for details. 3. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8.0 MHz. See Table 6-4 on page 25 for details.
Note that fuse bits are locked if Lock Bit 1 (LB1) is programmed. Fuse bits should be programmed before lock bits. The status of fuse bits is not affected by chip erase. Fuse bits can also be read by device firmware. See section "Reading the Fuse and Lock Bits from Software" on page 135. 19.2.1 Latching of Fuses Fuse values are latched when the device enters programming mode and changes to fuse values have no effect until the part leaves programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. Fuses are also latched on power-up.
19.3
Device Signature Imprint Table
The device signature imprint table is a dedicated memory area used for storing miscellaneous device information, such as the device signature and oscillator calibaration data. Most of this memory segment is reserved for internal use, as outlined in Table 19-6. Table 19-6.
Address 0x00 0x01 0x02 0x03 0x04 0x05 ... 0x2A Notes:
Contents of Device Signature Imprint Table.
High Byte Signature byte 0 (1) Calibration data for internal oscillator (2) Signature byte 1 (1) Reserved for internal use Signature byte 2 (1) Reserved for internal use
1. See section "Signature Bytes" for more information. 2. See section "Calibration Byte" for more information.
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19.3.1
Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and High-voltage Programming mode, also when the device is locked. Signature bytes can also be read by the device firmware. See section "Reading the Fuse and Lock Bits from Software" on page 135. The three signature bytes reside in a separate address space called the device signature imprint table. The signature data for ATTINY43U is given in Table 19-7. Table 19-7.
Part ATTINY43U
Device Signature Byte
Signature Byte 0 0x1E Signature Byte 1 0x92 Signature Byte 0 0x0C
19.3.2
Calibration Byte The device signature imprint table of ATTINY43U contains one byte of calibration data for the internal oscillator, as shown in Table 19-6 on page 141. During reset, this byte is automatically written into the OSCCAL register to ensure correct frequency of the calibrated oscillator. Calibration bytes can also be read by the device firmware. See section "Reading the Fuse and Lock Bits from Software" on page 135.
19.4
Page Size
Table 19-8.
Device ATTINY43U
No. of Words in a Page and No. of Pages in the Flash
Flash Size 2K words (4K bytes) Page Size 32 words PCWORD PC[4:0] No. of Pages 64 PCPAGE PC[10:5] PCMSB 10
Table 19-9.
Device ATTINY43U
No. of Words in a Page and No. of Pages in the EEPROM
EEPROM Size 64 bytes Page Size 4 bytes PCWORD EEA[1:0] No. of Pages 16 PCPAGE EEA[5:2] EEAMSB 5
19.5
Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATTINY43U. Pulses are assumed to be at least 250 ns unless otherwise noted.
19.5.1
Signal Names In this section, some pins of the ATTINY43U are referenced by signal names describing their functionality during parallel programming, see Figure 19-1 and Table 19-10. Pins not described in the following table are referenced by pin names.
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Figure 19-1. Parallel Programming
+5V WR XA0 XA1/BS2 PAGEL/BS1 OE RDY/BSY PA0 PA1 PA2 PA3 PA4 PA5 CLKI/PA6 +12 V RESET/PA7 GND
PB7 - PB0
VCC
DATA
Table 19-10. Pin Name Mapping
Signal Name in Programming Mode WR XA0 XA1/BS2 PAGEL/BS1 OE RDY/BSY DATA I/O Pin Name PA0 PA1 PA2 PA3 PA5 PA6 PB7-PB0 I/O I I I I I O I/O Function Write Pulse (Active low). CLKI Action Bit 0 CLKI Action Bit 1. Byte Select 2 ("0" selects low byte, "1" selects 2'nd high byte). Byte Select 1 ("0" selects low byte, "1" selects high byte). Program Memory and EEPROM Data Page Load. Output Enable (Active low). 0: Device is busy programming, 1: Device is ready for new command. Bi-directional Data bus (Output when OE is low).
Table 19-11. Pin Values Used to Enter Programming Mode
Pin PAGEL/BS1 XA1/BS2 XA0 WR Symbol Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] Value 0 0 0 0
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The XA1/XA0 pins determine the action executed when the CLKI pin is given a positive pulse. The bit coding is shown in Table 19-12. Table 19-12. XA1 and XA0 Coding
XA1 0 0 1 1 XA0 0 1 0 1 Action when CLKI is Pulsed Load Flash or EEPROM Address (High or low address byte determined by BS1). Load Data (High or Low data byte for Flash determined by BS1). Load Command No Action, Idle
When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 19-13. Table 19-13. Command Byte Bit Coding
Command Byte 1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Command Executed Chip Erase Write Fuse bits Write Lock bits Write Flash Write EEPROM Read Signature Bytes and Calibration byte Read Fuse and Lock bits Read Flash Read EEPROM
19.6
19.6.1
Parallel Programming
Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set RESET to "0" and toggle CLKI at least six times. 3. Set the Prog_enable pins listed in Table 19-11 on page 143 to "0000" and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering programming mode. 5. Wait at least 50 s before sending a new command.
19.6.2
Considerations for Efficient Programming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered.
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* The command needs only be loaded once when writing or reading multiple memory locations. * Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. * Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading. 19.6.3 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed.
Note: 1. The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
Load Command "Chip Erase" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS1 to "0". 3. Set DATA to "1000 0000". This is the command for Chip Erase. 4. Give CLKI a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. 19.6.4 Programming the Flash The Flash is organized in pages, see Table 19-8 on page 142. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command "Write Flash" 1. Set XA1, XA0 to "10". This enables command loading. 2. Set BS1 to "0". 3. Set DATA to "0001 0000". This is the command for Write Flash. 4. Give CLKI a positive pulse. This loads the command. B. Load Address Low byte 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "0". This selects low address. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give CLKI a positive pulse. This loads the address low byte. C. Load Data Low Byte 1. Set XA1, XA0 to "01". This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give CLKI a positive pulse. This loads the data byte. D. Load Data High Byte
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1. Set BS1 to "1". This selects high data byte. 2. Set XA1, XA0 to "01". This enables data loading. 3. Set DATA = Data high byte (0x00 - 0xFF). 4. Give CLKI a positive pulse. This loads the data byte. E. No action F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded. While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 19-2 on page 147. Note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write. G. Load Address High byte 1. Set XA1, XA0 to "00". This enables address loading. 2. Set BS1 to "1". This selects high address. 3. Set DATA = Address high byte (0x00 - 0xFF). 4. Give CLKI a positive pulse. This loads the address high byte. H. Program Page 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 2. Wait until RDY/BSY goes high (See Figure 19-3 for signal waveforms). I. Repeat B through H until the entire Flash is programmed or until all data has been programmed. J. End Page Programming 1. 1. Set XA1, XA0 to "10". This enables command loading. 2. Set DATA to "0000 0000". This is the command for No Operation. 3. Give CLKI a positive pulse. This loads the command, and the internal write signals are reset.
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Figure 19-2. Addressing the Flash Which is Organized in Pages(1)
PCMSB PROGRAM COUNTER
PCPAGE
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. PCPAGE and PCWORD are listed in Table 19-8 on page 142.
Figure 19-3. Programming the Flash Waveforms(1)
F A
DATA 0x10
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
G
ADDR. HIGH
H
XX
XA1/BS2
XA0
PAGEL/BS1
CLKI
WR
RDY/BSY
RESET +12V OE
Note:
1. "XX" is don't care. The letters refer to the programming description above.
19.6.5
Programming the EEPROM The EEPROM is organized in pages, see Table 19-9 on page 142. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to "Programming the Flash" on page 145 for details on Command, Address and Data loading): 1. A: Load Command "0001 0001". 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. C: Load Data (0x00 - 0xFF).
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5. E: No action. K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. Set BS1 to "0". 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (See Figure 19-4 for signal waveforms). Figure 19-4. Programming the EEPROM Waveforms
K
A
DATA 0x11
G
ADDR. HIGH
B
ADDR. LOW
C
DATA
E
XX
B
ADDR. LOW
C
DATA
E
XX
L
XA1/BS2
XA0
PAGEL/BS1
CLKI
WR
RDY/BSY
RESET +12V OE
19.6.6
Reading the Flash The algorithm for reading the Flash memory is as follows (refer to "Programming the Flash" on page 145 for details on Command and Address loading): 1. A: Load Command "0000 0010". 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to "0", and BS1 to "0". The Flash word low byte can now be read at DATA. 5. Set BS1 to "1". The Flash word high byte can now be read at DATA. 6. Set OE to "1".
19.6.7
Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to "Programming the Flash" on page 145 for details on Command and Address loading): 1. A: Load Command "0000 0011". 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to "0", and BS1 to "0". The EEPROM Data byte can now be read at DATA. 5. Set OE to "1".
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19.6.8
Programming the Fuse Low Bits The algorithm for programming the Fuse Low bits is as follows (refer to "Programming the Flash" on page 145 for details on Command and Data loading): 1. A: Load Command "0100 0000". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high.
19.6.9
Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to "Programming the Flash" on page 145 for details on Command and Data loading): 1. A: Load Command "0100 0000". 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. Set BS1 to "1" and BS2 to "0". This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to "0". This selects low data byte.
19.6.10
Programming the Extended Fuse Bits The algorithm for programming the Extended Fuse bits is as follows (refer to "Programming the Flash" on page 145 for details on Command and Data loading): 1. 1. A: Load Command "0100 0000". 2. 2. C: Load Data Low Byte. Bit n = "0" programs and bit n = "1" erases the Fuse bit. 3. 3. Set BS1 to "0" and BS2 to "1". This selects extended data byte. 4. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. 5. Set BS2 to "0". This selects low data byte. Figure 19-5. Programming the FUSES Waveforms
Write Fuse Low byte A
DATA
0x40
Write Fuse high byte A C
DATA XX
Write Extended Fuse byte A
0x40
C
DATA XX
C
DATA XX
0x40
XA1/BS2
XA0
PAGEL/BS1
CLKI
WR
RDY/BSY
RESET +12V OE
19.6.11
Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to "Programming the Flash" on page 145 for details on Command and Data loading):
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1. A: Load Command "0010 0000". 2. C: Load Data Low Byte. Bit n = "0" programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high. The Lock bits can only be cleared by executing Chip Erase. 19.6.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to "Programming the Flash" on page 145 for details on Command loading): 1. A: Load Command "0000 0100". 2. Set OE to "0", BS2 to "0" and BS1 to "0". The status of the Fuse Low bits can now be read at DATA ("0" means programmed). 3. Set OE to "0", BS2 to "1" and BS1 to "1". The status of the Fuse High bits can now be read at DATA ("0" means programmed). 4. Set OE to "0", BS2 to "1", and BS1 to "0". The status of the Extended Fuse bits can now be read at DATA ("0" means programmed). 5. Set OE to "0", BS2 to "0" and BS1 to "1". The status of the Lock bits can now be read at DATA ("0" means programmed). 6. Set OE to "1". Figure 19-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
Fuse Low Byte 0
0 Extended Fuse Byte BS2 Lock Bits 0 1 1 DATA
Fuse High Byte BS2
1
BS1
19.6.13
Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to "Programming the Flash" on page 145 for details on Command and Address loading): 1. A: Load Command "0000 1000". 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to "0", and BS to "0". The selected Signature byte can now be read at DATA. 4. Set OE to "1".
19.6.14
Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to "Programming the Flash" on page 145 for details on Command and Address loading):
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1. A: Load Command "0000 1000". 2. B: Load Address Low Byte, 0x00. 3. Set OE to "0", and BS1 to "1". The Calibration byte can now be read at DATA. 4. Set OE to "1".
19.7
Serial Programming
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). See Figure 19-7 below. Figure 19-7. Serial Programming and Verify
+1.8 - 5.5V VCC
MOSI MISO SCK
PB4 PB5 PB6
RESET/PA7
GND
Note:
If clocked by internal oscillator there is no need to connect a clock source to the CLKI pin.
After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed Table 19-14. Pin Mapping Serial Programming
Symbol MOSI MISO SCK Pins PB4 PB5 PB6 I/O I O I Description Serial Data in Serial Data out Serial Clock
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
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19.7.1
Serial Programming Algorithm When writing serial data to the ATTINY43U, data is clocked on the rising edge of SCK. When reading data from the ATTINY43U, data is clocked on the falling edge of SCK. See Figure 20-6 and Figure 20-7 for timing details. To program and verify the ATTINY43U in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in Table 19-16): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to "0". In some systems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to "0". 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The memory page is loaded one byte at a time by supplying the 5 LSB of the address and data together with the Load Program memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. The Program memory Page is stored by loading the Write Program memory Page instruction with the 3 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 19-15 on page 153.) Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming. 5. A: The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 19-15 on page 153.) In a chip erased device, no 0xFFs in the data file(s) need to be programmed. B: The EEPROM array is programmed one page at a time. The Memory page is loaded one byte at a time by supplying the 2 LSB of the address and data together with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by loading the Write EEPROM Memory Page Instruction with the 4 MSB of the address. When using EEPROM page access only byte locations loaded with the Load EEPROM Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the next page (See Table 19-15 on page 153). In a chip erased device, no 0xFF in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation.
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8. Power-off sequence (if needed): Set RESET to "1". Turn VCC power off. Table 19-15. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol tWD_FLASH tWD_EEPROM tWD_ERASE tWD_FUSE Minimum Wait Delay 4.5 ms 4.0 ms 4.0 ms 4.5 ms
19.7.2
Serial Programming Instruction set Table 19-16 on page 153 and Figure 19-8 on page 154 describes the Instruction set.
Table 19-16. Serial Programming Instruction Set
Instruction Format Instruction/Operation(1) Programming Enable Chip Erase (Program Memory/EEPROM) Poll RDY/BSY Load Instructions Load Extended Address byte Load Program Memory Page, High byte Load Program Memory Page, Low byte Load EEPROM Memory Page (page access) Read Instructions Read Program Memory, High byte Read Program Memory, Low byte Read EEPROM Memory Read Lock bits Read Signature Byte Read Fuse bits Read Fuse High bits Read Extended Fuse Bits Read Calibration Byte Write Instructions Write Program Memory Page Write EEPROM Memory Write EEPROM Memory Page (page access) Write Lock bits $4C $C0 $C2 $AC adr MSB $00 $00 $E0 adr LSB adr LSB adr LSB $00 $00 data byte in $00 data byte in $28 $20 $A0 $58 $30 $50 $58 $50 $38 adr MSB adr MSB $00 $00 $00 $00 $08 $08 $00 adr LSB adr LSB adr LSB $00 adr LSB $00 $00 $00 $00 high data byte out low data byte out data byte out data byte out data byte out data byte out data byte out data byte out data byte out $4D $48 $40 $C1 $00 adr MSB adr MSB $00 Extended adr adr LSB adr LSB adr LSB $00 high data byte in low data byte in data byte in Byte 1 $AC $AC $F0 Byte 2 $53 $80 $00 Byte 3 $00 $00 $00 Byte4 $00 $00 data byte out
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Table 19-16. Serial Programming Instruction Set (Continued)
Instruction Format Instruction/Operation Write Fuse bits Write Fuse High bits Write Extended Fuse Bits Notes: 1. 2. 3. 4. 5.
(1)
Byte 1 $AC $AC $AC
Byte 2 $A0 $A8 $A4
Byte 3 $00 $00 $00
Byte4 data byte in data byte in data byte in
Not all instructions are applicable for all parts. a = address Bits are programmed `0', unprogrammed `1'. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (`1') . Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.
If the LSB in RDY/BSY data byte out is `1', a programming operation is still pending. Wait until this bit returns `0' before the next instruction is carried out. Within the same page, the low data byte must be loaded prior to the high data byte. After data is loaded to the page buffer, program the EEPROM page, see Figure 19-8 on page 154. Figure 19-8. Serial Programming Instruction example
Serial Programming Instruction
Load Program Memory Page (High/Low Byte)/ Load EEPROM Memory Page (page access) Write Program Memory Page/ Write EEPROM Memory Page
Byte 1
Byte 2
Adr MSB Adr MSB r MS
Bit 15 B
Byte 3
Adr LSB
0
Byte 4
Byte 1
Byte 2
Adr MSB
Bit 15 B
Byte 3
Adr LS Adr LSB SB
0
Byte 4
Page Buffer
Page Offset
Page 0
Page 1
Page 2
Page Number
Page N-1
Program Memory/ EEPROM Memory
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20. Electrical Characteristics
20.1 Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Maximum Operating Voltage ............................................ 6.0V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 200.0 mA
20.2
Note:
DC Characteristics
All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary values representing design targets, and will be updated after characterization of actual silicon.
Table 20-1.
Symbol
DC Characteristics. TA = -40C to 85C
Parameter Input Low Voltage, Any Pin as I/O Condition VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V VCC = 1.8V - 5.5V VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V Min. -0.5 -0.5 -0.5 0.7VCC 0.6VCC 0.9 VCC
(3) (3) (3)
Typ.
Max. 0.2VCC
(1)
Units V V V V V V V V V V V V V V V
VIL Input Low Voltage, RESET Pin as Reset (2) Input High-voltage, Any Pin as I/O VIH Input High-voltage, RESET Pin as Reset (2) Output Low Voltage (4), Pins PB1, PB2, PB4 and PB5 (5) VOL Output Low Voltage (4), All Other I/O Pins, except RESET pin
0.3VCC (1) 0.2VCC (1) VCC +0.5 VCC +0.5 VCC +0.5 0.8 0.8 0.8 0.8 0.8 0.8
VCC = 1.8V to 5.5V
IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V IOL = 4 mA, VCC = 1.8V IOL = 10 mA, VCC = 5V IOL = 5 mA, VCC = 3V IOL = 2 mA, VCC = 1.8V IOH = 10 mA, VCC = 5V IOH = 5 mA, VCC = 3V IOH = 2 mA, VCC = 1.8V
4.0 2.3 1.4 -1 -1 1 1
VOH
Output High-voltage (6) All I/O Pins, except RESET pin Input Leakage Current, I/O Pin Input Leakage Current, I/O Pin
ILIL ILIH
VCC = 5.5V, pin low VCC = 5.5V, pin high
A A
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Table 20-1.
Symbol RPU
DC Characteristics. TA = -40C to 85C (Continued)
Parameter Pull-up Resistor, I/O Pin Pull-up Resistor, RESET Pin Supply Current, Active Mode, Without Boost Converter (7) Supply Current, Idle Mode, Without Boost Converter (7) Supply Current, Power-Down Mode, Without Boost Converter (7) Condition VCC = 5.5V, input low VCC = 5.5V, input low f = 1MHz, VCC = 2V f = 4MHz, VCC = 3V f = 8MHz, VCC = 5V f = 1MHz, VCC = 2V f = 4MHz, VCC = 3V f = 8MHz, VCC = 5V WDT enabled, VCC = 3V WDT disabled, VCC = 3V Min. 20 30 0.2 1.3 4 0.04 0.25 1.0 4.5 0.35 Typ. Max. 50 80 0.55 2.5 7 0.15 0.6 2.0 10 2 Units k k mA mA mA mA mA mA A A
ICC
Notes:
1. "Max" means the highest value where the pin is guaranteed to be read as low. 2. Not tested in production. 3. "Min" means the lowest value where the pin is guaranteed to be read as high. 4. Although each I/O port can under steady state (non-transient) conditions sink more than indicated, the sum of all IOL currents may not exceed 60 mA, or the boost converter limits. If IOL limits are exceeded the corresponding VOL levels can not be guaranteed. Pins are not guaranteed to sink currents greater than those listed. 5. Pins PB1, PB2, PB4 and PB5 are high sink I/O pins. 6. Although each I/O port can under steady state (non-transient) conditions source more than indicated, the sum of all IOH currents may not exceed 60 mA, or the boost converter limits. If IOH limits are exceeded the corresponding VOH levels can not be guaranteed. Pins are not guaranteed to source currents greater than those listed. 7. See "Boost Converter Characteristics" on page 159 for current consumption of entire device, including boost converter.
20.3
Speed Grades
Figure 20-1. Maximum Frequency vs. VCC (Boost Converter Disregarded).
8 MHz
Safe Operating Area
4 MHz
1.8V
2.7V
5.5V
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20.4
Clock Characteristics
20.4.1 Calibrated Internal Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Please note that the oscillator frequency depends on temperature and voltage. Table 20-2.
Calibration Method Factory Calibration User Calibration Notes:
Calibration Accuracy of Internal Oscillator
Target Frequency 8.0 MHz Fixed frequency within: 7.3 - 8.1 MHz VCC 3V Fixed voltage within: 1.8V - 5.5V Temperature 25C Fixed temperature within: -40C - 85C Accuracy at given Voltage & Temperature (1) 10% 1%
1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage).
20.4.2
External Clock Drive
Figure 20-2. External Clock Drive Waveforms
V IH1 V IL1
Table 20-3.
External Clock Drive Characteristics
VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V Min. 0 125 50 50 2.0 2.0 2 1.6 1.6 2 Max. 8 Units MHz ns ns ns s s %
Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL
Parameter Clock Frequency Clock Period High Time Low Time Rise Time Fall Time Period change from clock cycle to next
Min. 0 250 100 100
Max. 4
tCLCL
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20.5
System and Reset Characteristics
Reset, Brown-Out and Internal Voltage Characteristics
Parameter Power-on Reset Threshold Voltage (rising) Condition TA = -40 - 85C
(1)
Table 20-4.
Symbol VPOT VPSR VRST tRST VHYST tBOD VBG tBG IBG Note:
Min 1.1 0.6 0.01 0.2 VCC
Typ 1.4 1.3
Max 1.6 1.6
Units V V V/ms
Power-on Reset Threshold Voltage (falling) Power-On Slope Rate RESET Pin Threshold Minimum pulse width on RESET Pin Brown-out Detector Hysteresis Min Pulse Width on Brown-out Reset Internal bandgap reference voltage Internal bandgap reference start-up time
TA = -40 - 85C TA = -40 - 85C
0.9 VCC 2000 700 400 50 2
V ns mV s
VCC = 1.8V VCC = 3V VCC = 5V
VCC = 2.7V TA = 25C VCC = 2.7V TA = 25C VCC = 2.7V, TA = 25C
1.0
1.1 40 15
1.2 70
V s A
Internal bandgap reference current consumption
1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)
Table 20-5.
BODLEVEL Fuse Coding(1)
BODLEVEL [2..0] Fuses 111 110 101 100 011 010 Reserved 001 000 1.7 2.5 4.1 Min VBOT Typ VBOT BOD Disabled 1.8 2.7 4.3 2.0 2.9 4.5 V Max VBOT Units
Note:
1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed.
20.6
External Interrupt Characteristics
Characteristics of Asynchronous External Interrupt
Parameter Minimum pulse width for asynchronous external interrupt Condition Min Typ 50 Max Unit ns
Table 20-6.
Symbol tINT
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20.7
Boost Converter Characteristics
Characteristics of Boost Converter. T = -20C ... +85C, unless otherwise noted
Parameter Start Voltage Input Voltage Shutdown Voltage Condition Min 1.05 0.7 0.45 1.0 Output Voltage Active Mode, ILOAD > 1mA Low Current Mode Load Current Output Voltage Ripple Start-up Time VBAT = 0.7V VBAT = 1.0V VBAT = 1.0V, ILOAD = 30mA, CLOAD = 22F VBAT = Step Change from 0V to 1.2V VBAT = 0.45V, Converter in Stop Mode MCU not powered VBAT = 1.05V, Converter in Stop Mode MCU not powered VBAT = 1.2V, Active Low Current Mode MCU in Power Down, WD disabled VBAT = 1.2V, Active Regulated Mode MCU active, 4MHz 2.7 1.8 0 0 100 2 1 2 5 5 75 TS = 1 / fS 8 3 Output overload or short circuit removed TBD 1.05 100 10 125 13.3 72 TBD 3.0 3.3 3.6 10 30 Typ 1.2 Max 1.35 1.8 0.7 Unit V V V V V V mA mA mV ms A A A mA kHz s % V
Table 20-7.
Symbol VSTART VBAT VSTOP VBOOST VCC
ILOAD VRPP tSTART
IIN
Current consumption of entire device
fS TS DSW VBATOL
Switching frequency Switching period Duty Cycle Lowest VBAT voltage where device recovers from overload Load Regulation: V CC - V CC LOADMIN LOADMAX ----------------------------------------------------------------------------V CC
LOADMAX
T = 25C, VBAT = 1.2V Boost converter in Active Mode
2.7
%
Line Regulation: V CC - V CC VBATMAX VBATMIN --------------------------------------------------------------------------V CC
VBATNOM
T = 25C, ILOAD = 1mA Boost converter in Active Mode
1.0
%
Temperature Regulation: V CC - V CC TEMPMAX TEMPMIN ----------------------------------------------------------------------------V CC
TEMPNOM
VBAT = 1.2V, ILOAD = 1mA Boost converter in Active Mode
2.3
%
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20.8
ADC Characteristics - Preliminary Data
ADC Characteristics, Single_Ended Conversion, TA = -40C - 85C, Boost Converter Disabled.
Parameter Resolution VREF = 4V, VCC = 4V, ADC clock = 200 kHz VREF = 4V, VCC = 4V, ADC clock = 1 MHz VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode Integral Non-linearity (INL) (Accuracy after Offset and Gain Calibration) Differential Non-linearity (DNL) Gain Error Offset Error Conversion Time Clock Frequency VREF = 4V, VCC = 4V, ADC clock = 200 kHz VREF = 4V, VCC = 4V, ADC clock = 200 kHz VREF = 4V, VCC = 4V, ADC clock = 200 kHz VREF = 4V, VCC = 4V, ADC clock = 200 kHz Free Running Conversion 14 50 GND 38.4 1.0 1.1 100 1.2 4.0 5.0 Condition Min Typ Max 10 TBD TBD Units Bits LSB LSB
Table 20-8.
Symbol
Absolute accuracy (Including INL, DNL, and quantization, Gain and Offset Errors)
3.0
TBD
LSB
4.0
TBD
LSB
1.0
TBD
LSB
0.5 5.0 -3.0
TBD TBD TBD 280 1000 VREF
LSB LSB LSB s kHz V kHz V M
VIN
Input Voltage Input Bandwidth
VINT RAIN
Internal Voltage Reference Analog Input Resistance
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Table 20-9.
Symbol
ADC Characteristics, Single_Ended Conversion, TA = -40C - 85C, Boost Converter Enabled.
Parameter Resolution VREF = 4V, VCC = 4V, ADC clock = 200 kHz VREF = 4V, VCC = 4V, ADC clock = 1 MHz VREF = 4V, VCC = 4V, ADC clock = 200 kHz Noise Reduction Mode VREF = 4V, VCC = 4V, ADC clock = 1 MHz Noise Reduction Mode Integral Non-linearity (INL) (Accuracy after Offset and Gain Calibration) Differential Non-linearity (DNL) Gain Error Offset Error Conversion Time Clock Frequency VREF = 4V, VCC = 4V, ADC clock = 200 kHz VREF = 4V, VCC = 4V, ADC clock = 200 kHz VREF = 4V, VCC = 4V, ADC clock = 200 kHz VREF = 4V, VCC = 4V, ADC clock = 200 kHz Free Running Conversion 14 50 GND 38.4 1.0 1.1 100 1.2 TBD TBD Condition Min Typ Max 10 TBD TBD Units Bits LSB LSB
Absolute accuracy (Including INL, DNL, and quantization, Gain and Offset Errors)
TBD
TBD
LSB
TBD
TBD
LSB
TBD
TBD
LSB
TBD TBD TBD
TBD TBD TBD 280 1000 VREF
LSB LSB LSB s kHz V kHz V M
VIN
Input Voltage Input Bandwidth
VINT RAIN
Internal Voltage Reference Analog Input Resistance
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20.9
Parallel Programming Characteristics
Figure 20-3. Parallel Programming Timing, Including some General Timing Requirements
tXLWL CLKI tDVXH Data & Contol (DATA, XA0, XA1/BS2, PAGEL/BS1) tBVPH tPLBX t BVWL tWLWH WR RDY/BSY tWLRH tPLWL
WLRL
tXHXL tXLDX
tWLBX
Note:
The timing requirements in Figure 20-3 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.
Figure 20-4. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements
LOAD ADDRESS (LOW BYTE)
tXLOL
READ DATA (LOW BYTE)
READ DATA (HIGH BYTE)
LOAD ADDRESS (LOW BYTE)
CLKI
tBVDV
PAGEL/BS1
tOLDV
OE
tOHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1/BS2
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Figure 20-5. Parallel Programming Timing, Loading Sequence with Timing Requirements
LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE)
t XLXH
LOAD DATA (HIGH BYTE)
LOAD ADDRESS (LOW BYTE)
CLKI
PAGEL/BS1
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1/BS2
Table 20-10. Parallel Programming Characteristics, VCC = 5V 10%
Symbol VPP IPP tDVXH tXLXH tXHXL tXLDX tXLWL tBVPH tPHPL tPLBX tWLBX tPLWL tBVWL tWLWH tWLRL tWLRH tWLRH_CE tXLOL tBVDV tOLDV tOHDZ Note: 1. 2. Parameter Programming Enable Voltage Programming Enable Current Data and Control Valid before CLKI High CLKI Low to CLKI High CLKI Pulse Width High Data and Control Hold after CLKI Low CLKI Low to WR Low BS1 Valid before PAGEL High PAGEL Pulse Width High BS1 Hold after PAGEL Low BS2/1 Hold after WR Low PAGEL Low to WR Low BS1 Valid to WR Low WR Pulse Width Low WR Low to RDY/BSY Low WR Low to RDY/BSY High
(1)
Min 11.5
Typ
Max 12.5 250
Units V A ns ns ns ns ns ns ns ns ns ns ns ns
67 200 150 67 0 67 150 67 67 67 67 150 0 3.7 7.5 0 0 250 250 250 1 4.5 9
s ms ms ns ns ns ns
WR Low to RDY/BSY High for Chip Erase(2) CLKI Low to OE Low BS1 Valid to DATA valid OE Low to DATA Valid OE High to DATA Tri-stated
tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits commands. tWLRH_CE is valid for the Chip Erase command.
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20.10 Serial Programming Characteristics
Figure 20-6. Serial Programming Timing
MOSI tOVSH SCK MISO tSLIV
Figure 20-7. Serial Programming Waveforms
tSHOX tSHSL
tSLSH
SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK)
SAMPLE
MSB
LSB
MSB
LSB
Table 20-11. Serial Programming Characteristics, TA = -40C to 85C, VCC = 1.8 - 5.5V (Unless Otherwise Noted)
Symbol 1/tCLCL tCLCL 1/tCLCL tCLCL tSHSL tSLSH tOVSH tSHOX tSLIV Parameter Oscillator Frequency Oscillator Period Oscillator Frequency (VCC = 4.5V - 5.5V) Oscillator Period (VCC = 4.5V - 5.5V) SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High SCK Low to MISO Valid Min 0 250 0 125 2 tCLCL 2 tCLCL tCLCL 2 tCLCL TBD TBD TBD 8 Typ Max 4 Units MHz ns MHz ns ns ns ns ns ns
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21. Typical Characteristics - TBD
The data contained in this section is largely based on simulations and characterization of similar devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave. The following charts show typical behavior. These figures are not tested during manufacturing. During characterisation devices are operated at frequencies higher than test limits but they are not guaranteed to function properly at frequencies higher than the ordering code indicates. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. Current consumption is a function of several factors such as operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. A sine wave generator with rail-to-rail output is used as clock source but current consumption in Power-Down mode is independent of clock selection. The difference between current consumption in Power-Down mode with Watchdog Timer enabled and Power-Down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. The current drawn from pins with a capacitive load may be estimated (for one pin) as follows:
I CP V CC x C L x f SW
where VCC = operating voltage, CL = load capacitance and fSW = average switching frequency of I/O pin.
21.1
Boost Converter
Figure 21-1. Typical Transition Range Between Active Modes of Operation
TYPICAL TRANSITION RANGES BETWEEN MODES OF OPERATION
2.0
ACTIVE LOW CURRENT MODE
1.6
VBAT (V)
1.2
T AC
IVE
DE E D MO M OD LATE E NT EGU URR CTIVE R A WC LO
0.8
ACTIVE REGULATED MODE STOP MODE
0.4
0 0 0.1 0.2 0.3 0.4 Load Current (mA) 0.5 0.6 0.7
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Figure 21-2. Boost Converter Efficiency vs. Load Current and VBAT Voltage
BOOST CONVERTER EFFICIENCY vs. LOAD CURRENT
90
VBAT = 1.8 V
80 Efficiency (%)
VBAT = 1.5 V
VBAT = 1.2 V
70
VBAT = 1.0 V VBAT = 0.7 V
60 0 10 Load Current (mA) 20 30
Figure 21-3. Input Voltage Required to Maintain Regulation vs. Load Current
TYPICAL VBAT VOLTAGES REQUIRED TO MAINTAIN OUTPUT REGULATION
1.2
1.1
1.0 VBAT (V)
0.9
0.8
0.7
0.6 0 10 Load Current (mA) 20 30
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22. Register Summary
Address
0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
Name
SREG SPH SPL OCR0B GIMSK GIFR TIMSK0 TIFR0 SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL TCCR0A TCCR1A TCCR1B TCNT1 OCR1A OCR1B Reserved Reserved Reserved DWDR CLKPR Reserved Reserved GTCCR Reserved WDTCSR PCMSK1 Reserved EEAR EEDR EECR PORTA DDRA PINA PORTB DDRB PINB GPIOR2 GPIOR1 GPIOR0 PCMSK0 Reserved USIBR USIDR USISR USICR TIMSK1 TIFR1 Reserved Reserved ACSR ADMUX ADCSRA ADCH ADCL ADCSRB Reserved DIDR0 PRR
Bit 7
I - SP7 - - - - - BODS - FOC0A CAL7 COM0A1 COM1A1 FOC1A
Bit 6
T - SP6 INT0 INTF0 - - - PUD - FOC0B CAL6 COM0A0 COM1A0 FOC1B
Bit 5
H -
Bit 4
S -
Bit 3
V -
Bit 2
N -
Bit 1
Z - SP1 - - OCIE0A OCF0A PGERS ISC01 EXTRF CS01 CAL1 WGM01 WGM11
Bit 0
C SP8 SP0 - - TOIE0 TOV0 SPMEN ISC00 PORF CS00 CAL0 WGM00 WGM10 CS10
Page
Page 8 Page 12 Page 12 Page 95 Page 60 Page 60 Page 95 Page 96 Page 137 Page 95
Page 34, Page 59, Page 78
SP5 SP4 SP3 SP2 Timer/Counter0 - Output Compare Register B PCIE1 PCIF1 - - - PCIE0 PCIF0 - - - - - - - - OCIE0B OCF0B
CTPB RFLB PGWRT Timer/Counter0 - Output Compare Register A SM1 - - CAL4 COM0B0 COM1B0 - SM0 WDRF WGM02 CAL3 - - WGM12 CS12 BODSE BORF CS02 CAL2
SE - - CAL5 COM0B1 COM1B1 -
Page 54 Page 93 Page 94 Page 28 Page 90 Page 90 Page 93 Page 95 Page 95 Page 95
Timer/Counter0
CS11
Timer/Counter1 Timer/Counter1 - Output Compare Register A Timer/Counter1 - Output Compare Register B - - - DWDR[7:0] CLKPCE - - - - - TSM WDIF PCINT15 - - PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 - WDIE PCINT14 - - PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 - WDP3 PCINT13 EEAR5 EEPM1 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 - - WDCE PCINT12 - EEAR4 EEPM0 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 EEAR2 EEMPE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 EEAR1 EEPE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 WDE PCINT11 WDP2 PCINT10 WDP1 PCINT9 WDP0 PCINT8 - - - PSR10 CLKPS3 CLKPS2 CLKPS1 CLKPS0
Page 132 Page 28
Page 99 Page 54 Page 61 Page 20 Page 21 Page 21 Page 78 Page 78 Page 78 Page 78 Page 78 Page 78 Page 22 Page 22 Page 22
EEPROM Data Register
General Purpose I/O Register 2 General Purpose I/O Register 1 General Purpose I/O Register 0 PCINT7 PCINT6 PCINT5 PCINT4 - USI Buffer Register USI Data Register USISIF USISIE - - USIOIF USIOIE - - USIPF USIWM1 - - USIDC USIWM0 - - - - ACD - ADEN ACBG REFS ADSC ACO - ADATE ACI - ADIF ACIE - ADIE - MUX2 ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 USICNT3 USICS1 - - USICNT2 USICS0 OCIE1B OCF1B USICNT1 USICLK OCIE1A OCF1A USICNT0 USITC TOIE1 TOV1 PCINT3 PCINT2 PCINT1 PCINT0
Page 61 Page 111 Page 112 Page 112 Page 112 Page 96 Page 96
Page 113 Page 126 Page 127 Page 128 Page 128
ADC Data Register High Byte ADC Data Register Low Byte BS ACME - AIN1D PRE2 PRE1 PRE0 ADLAR - AIN0D - ADC3D PRTIM1 ADC2D PRTIM0 ADC1D PRUSI ADC0D PRADC - ADTS2 ADTS1 ADTS0
Pages 47, 113, 129 Page 114, Page 130 Page 35
167
8048B-AVR-03/09
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
168
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23. Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd Rd k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k Add two Registers
Description
Rd Rd + Rr
Operation
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1
ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Relative Jump Indirect Jump to (Z) Relative Subroutine Call Indirect Call to (Z) Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7)
BRANCH INSTRUCTIONS
BIT AND BIT-TEST INSTRUCTIONS
169
8048B-AVR-03/09
Mnemonics
ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH
Operands
Rd Rd Rd s s Rr, b Rd, b Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear
Description
Rotate Right Through Carry
Operation
Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (z) R1:R0 Rd P P Rr STACK Rr Rd STACK
Flags
Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 1 1 1 N/A
Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Rd, P P, Rr Rr Rd Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/Timer) For On-chip Debug Only
MCU CONTROL INSTRUCTIONS None None None
170
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24. Ordering Information
24.1 ATTINY43U
Power Supply 1.8 - 5.5V (3) Ordering Code (1) ATTINY43U-MU ATTINY43U-SU Package (2) 20M1 20S2 Operational Range Industrial (-40C to 85C) Speed (MHz) 8 Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Supply voltage on VCC pin, boost converter disregarded. When boost converter is active the device can be operated from voltages sources lower than indicated here. See table "Characteristics of Boost Converter. T = -20C ... +85C, unless otherwise noted" on page 159 for more information.
Package Type 20M1 20S2 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
171
8048B-AVR-03/09
25. Packaging Information
25.1 20M1
D
1 Pin 1 ID 2 3
E
SIDE VIEW
TOP VIEW A2 D2 A1 A
1 Pin #1 Notch (0.20 R) 2 3
0.08
C
E2
SYMBOL A A1
COMMON DIMENSIONS (Unit of Measure = mm) MIN 0.70 - NOM 0.75 0.01 0.20 REF 0.18 0.23 4.00 BSC 2.45 2.60 4.00 BSC 2.45 2.60 0.50 BSC 0.35 0.40 0.55 2.75 2.75 0.30 MAX 0.80 0.05 NOTE
b
L e BOTTOM VIEW
A2 b D D2 E E2 e
Note:
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
L
10/27/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 20M1 REV. A
R
172
ATTINY43U
8048B-AVR-03/09
25.2
20S2
173
8048B-AVR-03/09
26. Errata
The revision letter in this section refers to the revision of the ATTINY43U device.
26.1
26.1.1
ATTINY43U
Rev. C * Increased Probability of Boost Converter Entering Active Low Current Mode 1. Increased Probability of Boost Converter Entering Active Low Current Mode The boost converter may enter and stay in Active Low Current Mode at supply voltages and load currents higher than those specified. This is due to high switching currents in bonding wires of the SOIC package. Devices packaged in MLF are not affected. Problem Fix / Workaround Add a 1.5nF capacitor between pins LSW and GND of the SOIC package. Also, increase the value of the by-pass capacitor between pins VCC and GND to at least 30F. Alternatively, use the device in MLF, without modifications.
26.1.2
Rev. B Not sampled.
26.1.3
Rev. A Not sampled.
174
ATTINY43U
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27. Datasheet Revision History
27.1 Rev. 8048B-03/09
1.
Updated Data retention bullet in "Features" on page 1.
27.2
Rev. 8048A-02/09
1.
Initial revision.
175
8048B-AVR-03/09
176
ATTINY43U
8048B-AVR-03/09
Table of Contents
Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2
1.1 Pin Descriptions .................................................................................................2
2 3
Overview ................................................................................................... 4 About ......................................................................................................... 6
3.1 3.2 3.3 3.4 Resources .........................................................................................................6 Code Examples .................................................................................................6 Data Retention ...................................................................................................6 Disclaimer ..........................................................................................................6
4
AVR CPU Core .......................................................................................... 7
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Introduction ........................................................................................................7 Architectural Overview .......................................................................................7 ALU - Arithmetic Logic Unit ...............................................................................8 Status Register ..................................................................................................8 General Purpose Register File ........................................................................10 Stack Pointer ...................................................................................................11 Instruction Execution Timing ...........................................................................12 Reset and Interrupt Handling ...........................................................................13
5
Memories ................................................................................................ 15
5.1 5.2 5.3 5.4 5.5 5.6 Overview ..........................................................................................................15 In-System Re-programmable Flash Program Memory ....................................15 SRAM Data Memory ........................................................................................15 EEPROM Data Memory ..................................................................................16 I/O Memory ......................................................................................................20 Register Description ........................................................................................20
6
System Clock and Clock Options ......................................................... 23
6.1 6.2 6.3 6.4 6.5 Clock Systems and their Distribution ...............................................................23 Clock Sources .................................................................................................24 System Clock Prescaler ..................................................................................27 Clock Output Buffer .........................................................................................28 Register Description ........................................................................................28
7
Power Management and Sleep Modes ................................................. 31
i
8048B-AVR-03/09
7.1 7.2 7.3 7.4 7.5
Sleep Modes ....................................................................................................31 Software BOD Disable .....................................................................................32 Power Reduction Register ...............................................................................32 Minimizing Power Consumption ......................................................................33 Register Description ........................................................................................34
8
Power Supply and On-Chip Boost Converter ...................................... 36
8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 Overview ..........................................................................................................36 Modes of Operation .........................................................................................37 Output Voltage versus Load Current ...............................................................40 Overload Behaviour .........................................................................................42 Software Control of Boost Converter ...............................................................42 Component Selection ......................................................................................43 Typical Applications .........................................................................................46 Characteristics .................................................................................................46 Potential Limitations ........................................................................................46 Bypassing the Boost Converter .......................................................................46 Register Description ........................................................................................47
9
System Control and Reset .................................................................... 48
9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Resetting the AVR ...........................................................................................48 Reset Sources .................................................................................................49 Power-on Reset ...............................................................................................49 External Reset .................................................................................................50 Brown-out Detection ........................................................................................50 Watchdog Reset ..............................................................................................51 Internal Voltage Reference ..............................................................................51 Watchdog Timer ..............................................................................................51 Register Description ........................................................................................54
10 Interrupts ................................................................................................ 57
10.1 10.2 10.3 Interrupt Vectors ..............................................................................................57 External Interrupts ...........................................................................................58 Register Description ........................................................................................59
11 I/O Ports .................................................................................................. 62
11.1 11.2 11.3 ii Introduction ......................................................................................................62 Ports as General Digital I/O .............................................................................63 Alternate Port Functions ..................................................................................67
ATTINY43U
8048B-AVR-03/09
11.4
Register Description ........................................................................................78
12 8-bit Timer/Counter with PWM (Timer/Counter0 and Timer/Counter1) . 79
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Features ..........................................................................................................79 Overview ..........................................................................................................79 Timer/Counter Clock Sources .........................................................................80 Counter Unit ....................................................................................................80 Output Compare Unit .......................................................................................81 Compare Match Output Unit ............................................................................83 Modes of Operation .........................................................................................84 Timer/Counter Timing Diagrams .....................................................................88 Register Description ........................................................................................90
13 Timer/Counter Prescaler ....................................................................... 98
13.1 13.2 13.3 Prescaler Reset ...............................................................................................98 External Clock Source .....................................................................................98 Register Description ........................................................................................99
14 USI - Universal Serial Interface .......................................................... 100
14.1 14.2 14.3 14.4 14.5 Features ........................................................................................................100 Overview ........................................................................................................100 Functional Descriptions .................................................................................101 Alternative USI Usage ...................................................................................107 Register Descriptions ....................................................................................107
15 Analog Comparator ............................................................................. 112
15.1 15.2 Analog Comparator Multiplexed Input ...........................................................112 Register Description ......................................................................................113
16 Analog to Digital Converter ................................................................ 115
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 Features ........................................................................................................115 Overview ........................................................................................................115 ADC Operation ..............................................................................................116 Starting a Conversion ....................................................................................116 Prescaling and Conversion Timing ................................................................117 Changing Channel or Reference Selection ...................................................120 ADC Noise Canceler .....................................................................................121 Analog Input Circuitry ....................................................................................122 Analog Noise Canceling Techniques .............................................................122 iii
8048B-AVR-03/09
16.10 16.11 16.12 16.13
ADC Accuracy Definitions .............................................................................123 ADC Conversion Result .................................................................................125 Temperature Measurement ...........................................................................125 Register Description ......................................................................................126
17 debugWIRE On-chip Debug System .................................................. 131
17.1 17.2 17.3 17.4 17.5 17.6 Features ........................................................................................................131 Overview ........................................................................................................131 Physical Interface ..........................................................................................131 Software Break Points ...................................................................................132 Limitations of debugWIRE .............................................................................132 Register Description ......................................................................................132
18 Self-Programming the Flash ............................................................... 133
18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 Performing Page Erase by SPM ....................................................................133 Filling the Temporary Buffer (Page Loading) .................................................133 Performing a Page Write ...............................................................................134 Addressing the Flash During Self-Programming ...........................................134 EEPROM Write Prevents Writing to SPMCSR ..............................................135 Reading the Fuse and Lock Bits from Software ............................................135 Preventing Flash Corruption ..........................................................................137 Programming Time for Flash when Using SPM ............................................137 Register Description ......................................................................................137
19 Memory Programming ......................................................................... 139
19.1 19.2 19.3 19.4 19.5 19.6 19.7 Program And Data Memory Lock Bits ...........................................................139 Fuse Bytes .....................................................................................................140 Device Signature Imprint Table .....................................................................141 Page Size ......................................................................................................142 Parallel Programming Parameters, Pin Mapping, and Commands ...............142 Parallel Programming ....................................................................................144 Serial Programming .......................................................................................151
20 Electrical Characteristics .................................................................... 155
20.1 20.2 20.3 20.4 20.5 iv Absolute Maximum Ratings* .........................................................................155 DC Characteristics .........................................................................................155 Speed Grades ...............................................................................................156 Clock Characteristics .....................................................................................157 System and Reset Characteristics ................................................................158
ATTINY43U
8048B-AVR-03/09
20.6 20.7 20.8 20.9 20.10
External Interrupt Characteristics ..................................................................158 Boost Converter Characteristics ....................................................................159 ADC Characteristics - Preliminary Data ........................................................160 Parallel Programming Characteristics ...........................................................162 Serial Programming Characteristics ..............................................................164
21 Typical Characteristics - TBD ............................................................ 165
21.1 Boost Converter .............................................................................................165
22 Register Summary ............................................................................... 167 23 Instruction Set Summary .................................................................... 169 24 Ordering Information ........................................................................... 171
24.1 ATTINY43U ......................................................................................................171
25 Packaging Information ........................................................................ 172
25.1 25.2 20M1 ..............................................................................................................172 20S2 ..............................................................................................................173
26 Errata ..................................................................................................... 174
26.1 ATTINY43U ......................................................................................................174
27 Datasheet Revision History ................................................................ 175
27.1 27.2 Rev. 8048B-03/09 ..........................................................................................175 Rev. 8048A-02/09 ..........................................................................................175
Table of Contents....................................................................................... i
v
8048B-AVR-03/09
Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
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8048B-AVR-03/09

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